Weiming Zhao 8d5c72d513 This patch eanble register coalescing to coalesce the following: ...

%vreg2<def> = MOVi32imm 1; GPR32:%vreg2
  %W1<def> = COPY %vreg2; GPR32:%vreg2
into:
  %W1<def> = MOVi32imm 1
Patched by Lawrence Hu (lawrence@codeaurora.org)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243033 91177308-0d34-0410-b5e6-96231b3b80d8

2015-07-23 19:24:53 +00:00

..

AArch64

This patch eanble register coalescing to coalesce the following:

2015-07-23 19:24:53 +00:00

AMDGPU

AMDGPU/SI: Add VI patterns to select FLAT instructions for global memory ops

2015-07-20 14:28:41 +00:00

ARM

[ARM] Make the frame lowering code ready for shrink-wrapping.

2015-07-22 16:34:37 +00:00

BPF

…

CPP

…

Generic

Targets: commonize some stack realignment code

2015-07-20 22:51:32 +00:00

Hexagon

[Hexagon] Generate MUX from conditional transfers when dot-new not possible

2015-07-20 21:23:25 +00:00

Inputs

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Mips

[SDAG] Optimize unordered comparison in soft-float mode (patch by Anton Nadolskiy)

2015-07-15 08:39:35 +00:00

MIR

MIR Serialization: Serialize the machine instruction's debug location.

2015-07-22 21:15:11 +00:00

MSP430

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NVPTX

[BranchFolding] do not iterate the aliases of virtual registers

2015-07-22 04:16:52 +00:00

PowerPC

[PPC64LE] More vector swap optimization TLC

2015-07-21 21:40:17 +00:00

SPARC

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SystemZ

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Thumb

[ARM] Make the frame lowering code ready for shrink-wrapping.

2015-07-22 16:34:37 +00:00

Thumb2

ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2

2015-07-21 00:18:59 +00:00

WebAssembly

WebAssembly: basic bitcode → assembly CodeGen test

2015-07-22 21:28:15 +00:00

WinEH

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X86

[X86] Allow load folding into PUSH instructions

2015-07-23 12:23:45 +00:00

XCore

…