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https://github.com/c64scene-ar/llvm-6502.git
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ba59a1e453
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32098 91177308-0d34-0410-b5e6-96231b3b80d8
64 lines
2.1 KiB
C++
64 lines
2.1 KiB
C++
//===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Constant.h"
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#include "llvm/DerivedTypes.h"
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using namespace llvm;
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TargetInstrInfo::TargetInstrInfo(const TargetInstrDescriptor* Desc,
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unsigned numOpcodes)
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: desc(Desc), NumOpcodes(numOpcodes) {
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}
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TargetInstrInfo::~TargetInstrInfo() {
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}
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/// findTiedToSrcOperand - Returns the operand that is tied to the specified
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/// dest operand. Returns -1 if there isn't one.
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int
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TargetInstrInfo::findTiedToSrcOperand(MachineOpCode Opc, unsigned OpNum) const {
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for (unsigned i = 0, e = getNumOperands(Opc); i != e; ++i) {
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if (i == OpNum)
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continue;
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int ti = getOperandConstraint(Opc, i, TOI::TIED_TO);
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if (ti == (int)OpNum)
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return i;
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}
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return -1;
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}
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// commuteInstruction - The default implementation of this method just exchanges
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// operand 1 and 2.
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MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI) const {
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assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() &&
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"This only knows how to commute register operands so far");
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unsigned Reg1 = MI->getOperand(1).getReg();
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unsigned Reg2 = MI->getOperand(2).getReg();
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bool Reg1IsKill = MI->getOperand(1).isKill();
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bool Reg2IsKill = MI->getOperand(2).isKill();
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MI->getOperand(2).setReg(Reg1);
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MI->getOperand(1).setReg(Reg2);
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if (Reg1IsKill)
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MI->getOperand(2).setIsKill();
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else
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MI->getOperand(2).unsetIsKill();
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if (Reg2IsKill)
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MI->getOperand(1).setIsKill();
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else
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MI->getOperand(1).unsetIsKill();
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return MI;
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}
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