mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-22 09:29:31 +00:00
a9a94ce839
TableGen has a fairly dubious heuristic to decide whether an alias should be printed: does the alias have lest operands than the real instruction. This is bad enough (particularly with no way to override it), but it should at least be calculated consistently for both strings. This patch implements that logic: first get the *correct* string for the variant, in the same way as the Matcher, without guessing; then count the number of whitespace chars. There are basically 4 changes this brings about after the previous commits; all of these appear to be good, so I have changed the tests: + ARM64: we print "neg X, Y" instead of "sub X, xzr, Y". + ARM64: we skip implicit "uxtx" and "uxtw" modifiers. + Sparc: we print "mov A, B" instead of "or %g0, A, B". + Sparc: we print "fcmpX A, B" instead of "fcmpX %fcc0, A, B" git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208969 91177308-0d34-0410-b5e6-96231b3b80d8
100 lines
2.2 KiB
LLVM
100 lines
2.2 KiB
LLVM
;RUN: llc -march=sparc < %s | FileCheck %s -check-prefix=V8
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;RUN: llc -march=sparc -mattr=v9 < %s | FileCheck %s -check-prefix=V9
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;RUN: llc -march=sparc -regalloc=basic < %s | FileCheck %s -check-prefix=V8
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;RUN: llc -march=sparc -regalloc=basic -mattr=v9 < %s | FileCheck %s -check-prefix=V9
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;RUN: llc -march=sparcv9 < %s | FileCheck %s -check-prefix=SPARC64
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define i8* @frameaddr() nounwind readnone {
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entry:
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;V8-LABEL: frameaddr:
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;V8: save %sp, -96, %sp
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;V8: ret
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;V8: restore %g0, %fp, %o0
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;V9-LABEL: frameaddr:
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;V9: save %sp, -96, %sp
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;V9: ret
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;V9: restore %g0, %fp, %o0
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;SPARC64-LABEL: frameaddr
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;SPARC64: save %sp, -128, %sp
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;SPARC64: add %fp, 2047, %i0
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;SPARC64: ret
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;SPARC64-NOT: restore %g0, %g0, %g0
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;SPARC64: restore
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%0 = tail call i8* @llvm.frameaddress(i32 0)
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ret i8* %0
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}
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define i8* @frameaddr2() nounwind readnone {
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entry:
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;V8-LABEL: frameaddr2:
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;V8: ta 3
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;V8: ld [%fp+56], {{.+}}
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;V8: ld [{{.+}}+56], {{.+}}
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;V8: ld [{{.+}}+56], {{.+}}
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;V9-LABEL: frameaddr2:
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;V9: flushw
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;V9: ld [%fp+56], {{.+}}
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;V9: ld [{{.+}}+56], {{.+}}
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;V9: ld [{{.+}}+56], {{.+}}
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;SPARC64-LABEL: frameaddr2
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;SPARC64: flushw
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;SPARC64: ldx [%fp+2159], %[[R0:[goli][0-7]]]
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;SPARC64: ldx [%[[R0]]+2159], %[[R1:[goli][0-7]]]
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;SPARC64: ldx [%[[R1]]+2159], %[[R2:[goli][0-7]]]
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;SPARC64: add %[[R2]], 2047, {{.+}}
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%0 = tail call i8* @llvm.frameaddress(i32 3)
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ret i8* %0
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}
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declare i8* @llvm.frameaddress(i32) nounwind readnone
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define i8* @retaddr() nounwind readnone {
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entry:
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;V8-LABEL: retaddr:
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;V8: mov %o7, {{.+}}
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;V9-LABEL: retaddr:
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;V9: mov %o7, {{.+}}
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;SPARC64-LABEL: retaddr
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;SPARC64: mov %o7, {{.+}}
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%0 = tail call i8* @llvm.returnaddress(i32 0)
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ret i8* %0
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}
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define i8* @retaddr2() nounwind readnone {
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entry:
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;V8-LABEL: retaddr2:
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;V8: ta 3
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;V8: ld [%fp+56], {{.+}}
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;V8: ld [{{.+}}+56], {{.+}}
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;V8: ld [{{.+}}+60], {{.+}}
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;V9-LABEL: retaddr2:
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;V9: flushw
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;V9: ld [%fp+56], {{.+}}
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;V9: ld [{{.+}}+56], {{.+}}
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;V9: ld [{{.+}}+60], {{.+}}
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;SPARC64-LABEL: retaddr2
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;SPARC64: flushw
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;SPARC64: ldx [%fp+2159], %[[R0:[goli][0-7]]]
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;SPARC64: ldx [%[[R0]]+2159], %[[R1:[goli][0-7]]]
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;SPARC64: ldx [%[[R1]]+2167], {{.+}}
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%0 = tail call i8* @llvm.returnaddress(i32 3)
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ret i8* %0
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}
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declare i8* @llvm.returnaddress(i32) nounwind readnone
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