mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143891 91177308-0d34-0410-b5e6-96231b3b80d8
458 lines
16 KiB
C++
458 lines
16 KiB
C++
//===-- MipsAsmPrinter.cpp - Mips LLVM assembly writer --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a printer that converts from our internal representation
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// of machine-dependent LLVM code to GAS-format MIPS assembly language.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mips-asm-printer"
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#include "MipsAsmPrinter.h"
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#include "Mips.h"
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#include "MipsInstrInfo.h"
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#include "MipsMachineFunction.h"
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#include "MipsMCInstLower.h"
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#include "MipsMCSymbolRefExpr.h"
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#include "InstPrinter/MipsInstPrinter.h"
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#include "llvm/BasicBlock.h"
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#include "llvm/Instructions.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Target/Mangler.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetLoweringObjectFile.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/ADT/SmallString.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Analysis/DebugInfo.h"
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using namespace llvm;
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static bool isUnalignedLoadStore(unsigned Opc) {
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return Opc == Mips::ULW || Opc == Mips::ULH || Opc == Mips::ULHu ||
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Opc == Mips::USW || Opc == Mips::USH ||
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Opc == Mips::ULW_P8 || Opc == Mips::ULH_P8 || Opc == Mips::ULHu_P8 ||
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Opc == Mips::USW_P8 || Opc == Mips::USH_P8;
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}
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void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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SmallString<128> Str;
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raw_svector_ostream OS(Str);
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if (MI->isDebugValue()) {
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PrintDebugValueComment(MI, OS);
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return;
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}
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MipsMCInstLower MCInstLowering(Mang, *MF, *this);
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unsigned Opc = MI->getOpcode();
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MCInst TmpInst0;
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MCInstLowering.Lower(MI, TmpInst0);
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// Enclose unaligned load or store with .macro & .nomacro directives.
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if (isUnalignedLoadStore(Opc)) {
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MCInst Directive;
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Directive.setOpcode(Mips::MACRO);
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OutStreamer.EmitInstruction(Directive);
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OutStreamer.EmitInstruction(TmpInst0);
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Directive.setOpcode(Mips::NOMACRO);
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OutStreamer.EmitInstruction(Directive);
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return;
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}
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OutStreamer.EmitInstruction(TmpInst0);
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}
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//===----------------------------------------------------------------------===//
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//
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// Mips Asm Directives
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//
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// -- Frame directive "frame Stackpointer, Stacksize, RARegister"
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// Describe the stack frame.
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//
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// -- Mask directives "(f)mask bitmask, offset"
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// Tells the assembler which registers are saved and where.
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// bitmask - contain a little endian bitset indicating which registers are
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// saved on function prologue (e.g. with a 0x80000000 mask, the
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// assembler knows the register 31 (RA) is saved at prologue.
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// offset - the position before stack pointer subtraction indicating where
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// the first saved register on prologue is located. (e.g. with a
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//
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// Consider the following function prologue:
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//
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// .frame $fp,48,$ra
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// .mask 0xc0000000,-8
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// addiu $sp, $sp, -48
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// sw $ra, 40($sp)
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// sw $fp, 36($sp)
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//
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// With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
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// 30 (FP) are saved at prologue. As the save order on prologue is from
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// left to right, RA is saved first. A -8 offset means that after the
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// stack pointer subtration, the first register in the mask (RA) will be
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// saved at address 48-8=40.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Mask directives
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//===----------------------------------------------------------------------===//
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// Create a bitmask with all callee saved registers for CPU or Floating Point
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// registers. For CPU registers consider RA, GP and FP for saving if necessary.
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void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) {
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// CPU and FPU Saved Registers Bitmasks
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unsigned CPUBitmask = 0, FPUBitmask = 0;
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int CPUTopSavedRegOff, FPUTopSavedRegOff;
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// Set the CPU and FPU Bitmasks
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const MachineFrameInfo *MFI = MF->getFrameInfo();
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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// size of stack area to which FP callee-saved regs are saved.
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unsigned CPURegSize = Mips::CPURegsRegisterClass->getSize();
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unsigned FGR32RegSize = Mips::FGR32RegisterClass->getSize();
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unsigned AFGR64RegSize = Mips::AFGR64RegisterClass->getSize();
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bool HasAFGR64Reg = false;
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unsigned CSFPRegsSize = 0;
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unsigned i, e = CSI.size();
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// Set FPU Bitmask.
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for (i = 0; i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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if (Mips::CPURegsRegisterClass->contains(Reg))
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break;
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unsigned RegNum = MipsRegisterInfo::getRegisterNumbering(Reg);
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if (Mips::AFGR64RegisterClass->contains(Reg)) {
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FPUBitmask |= (3 << RegNum);
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CSFPRegsSize += AFGR64RegSize;
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HasAFGR64Reg = true;
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continue;
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}
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FPUBitmask |= (1 << RegNum);
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CSFPRegsSize += FGR32RegSize;
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}
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// Set CPU Bitmask.
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for (; i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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unsigned RegNum = MipsRegisterInfo::getRegisterNumbering(Reg);
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CPUBitmask |= (1 << RegNum);
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}
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// FP Regs are saved right below where the virtual frame pointer points to.
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FPUTopSavedRegOff = FPUBitmask ?
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(HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
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// CPU Regs are saved below FP Regs.
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CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
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// Print CPUBitmask
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O << "\t.mask \t"; printHex32(CPUBitmask, O);
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O << ',' << CPUTopSavedRegOff << '\n';
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// Print FPUBitmask
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O << "\t.fmask\t"; printHex32(FPUBitmask, O);
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O << "," << FPUTopSavedRegOff << '\n';
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}
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// Print a 32 bit hex number with all numbers.
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void MipsAsmPrinter::printHex32(unsigned Value, raw_ostream &O) {
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O << "0x";
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for (int i = 7; i >= 0; i--)
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O.write_hex((Value & (0xF << (i*4))) >> (i*4));
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}
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//===----------------------------------------------------------------------===//
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// Frame and Set directives
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//===----------------------------------------------------------------------===//
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/// Frame Directive
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void MipsAsmPrinter::emitFrameDirective() {
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const TargetRegisterInfo &RI = *TM.getRegisterInfo();
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unsigned stackReg = RI.getFrameRegister(*MF);
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unsigned returnReg = RI.getRARegister();
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unsigned stackSize = MF->getFrameInfo()->getStackSize();
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OutStreamer.EmitRawText("\t.frame\t$" +
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StringRef(MipsInstPrinter::getRegisterName(stackReg)).lower() +
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"," + Twine(stackSize) + ",$" +
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StringRef(MipsInstPrinter::getRegisterName(returnReg)).lower());
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}
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/// Emit Set directives.
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const char *MipsAsmPrinter::getCurrentABIString() const {
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switch (Subtarget->getTargetABI()) {
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case MipsSubtarget::O32: return "abi32";
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case MipsSubtarget::N32: return "abiN32";
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case MipsSubtarget::N64: return "abi64";
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case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64
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default: break;
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}
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llvm_unreachable("Unknown Mips ABI");
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return NULL;
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}
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void MipsAsmPrinter::EmitFunctionEntryLabel() {
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OutStreamer.EmitRawText("\t.ent\t" + Twine(CurrentFnSym->getName()));
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OutStreamer.EmitLabel(CurrentFnSym);
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}
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/// EmitFunctionBodyStart - Targets can override this to emit stuff before
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/// the first basic block in the function.
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void MipsAsmPrinter::EmitFunctionBodyStart() {
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emitFrameDirective();
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SmallString<128> Str;
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raw_svector_ostream OS(Str);
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printSavedRegsBitmask(OS);
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OutStreamer.EmitRawText(OS.str());
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}
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/// EmitFunctionBodyEnd - Targets can override this to emit stuff after
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/// the last basic block in the function.
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void MipsAsmPrinter::EmitFunctionBodyEnd() {
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// There are instruction for this macros, but they must
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// always be at the function end, and we can't emit and
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// break with BB logic.
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OutStreamer.EmitRawText(StringRef("\t.set\tmacro"));
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OutStreamer.EmitRawText(StringRef("\t.set\treorder"));
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OutStreamer.EmitRawText("\t.end\t" + Twine(CurrentFnSym->getName()));
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}
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/// isBlockOnlyReachableByFallthough - Return true if the basic block has
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/// exactly one predecessor and the control transfer mechanism between
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/// the predecessor and this block is a fall-through.
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bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
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MBB) const {
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// The predecessor has to be immediately before this block.
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const MachineBasicBlock *Pred = *MBB->pred_begin();
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// If the predecessor is a switch statement, assume a jump table
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// implementation, so it is not a fall through.
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if (const BasicBlock *bb = Pred->getBasicBlock())
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if (isa<SwitchInst>(bb->getTerminator()))
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return false;
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// If this is a landing pad, it isn't a fall through. If it has no preds,
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// then nothing falls through to it.
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if (MBB->isLandingPad() || MBB->pred_empty())
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return false;
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// If there isn't exactly one predecessor, it can't be a fall through.
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MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
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++PI2;
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if (PI2 != MBB->pred_end())
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return false;
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// The predecessor has to be immediately before this block.
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if (!Pred->isLayoutSuccessor(MBB))
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return false;
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// If the block is completely empty, then it definitely does fall through.
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if (Pred->empty())
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return true;
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// Otherwise, check the last instruction.
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// Check if the last terminator is an unconditional branch.
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MachineBasicBlock::const_iterator I = Pred->end();
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while (I != Pred->begin() && !(--I)->getDesc().isTerminator()) ;
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return !I->getDesc().isBarrier();
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}
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// Print out an operand for an inline asm expression.
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bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant,const char *ExtraCode,
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raw_ostream &O) {
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// Does this asm operand have a single letter operand modifier?
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if (ExtraCode && ExtraCode[0])
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return true; // Unknown modifier.
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printOperand(MI, OpNo, O);
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return false;
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}
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bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
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unsigned OpNum, unsigned AsmVariant,
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const char *ExtraCode,
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raw_ostream &O) {
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if (ExtraCode && ExtraCode[0])
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return true; // Unknown modifier.
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const MachineOperand &MO = MI->getOperand(OpNum);
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assert(MO.isReg() && "unexpected inline asm memory operand");
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O << "0($" << MipsInstPrinter::getRegisterName(MO.getReg()) << ")";
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return false;
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}
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void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
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raw_ostream &O) {
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const MachineOperand &MO = MI->getOperand(opNum);
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bool closeP = false;
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if (MO.getTargetFlags())
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closeP = true;
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switch(MO.getTargetFlags()) {
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case MipsII::MO_GPREL: O << "%gp_rel("; break;
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case MipsII::MO_GOT_CALL: O << "%call16("; break;
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case MipsII::MO_GOT: O << "%got("; break;
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case MipsII::MO_ABS_HI: O << "%hi("; break;
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case MipsII::MO_ABS_LO: O << "%lo("; break;
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case MipsII::MO_TLSGD: O << "%tlsgd("; break;
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case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
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case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
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case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
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case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break;
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case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break;
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case MipsII::MO_GOT_DISP: O << "%got_disp("; break;
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case MipsII::MO_GOT_PAGE: O << "%got_page("; break;
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case MipsII::MO_GOT_OFST: O << "%got_ofst("; break;
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}
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switch (MO.getType()) {
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case MachineOperand::MO_Register:
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O << '$'
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<< StringRef(MipsInstPrinter::getRegisterName(MO.getReg())).lower();
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break;
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case MachineOperand::MO_Immediate:
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O << MO.getImm();
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break;
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case MachineOperand::MO_MachineBasicBlock:
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O << *MO.getMBB()->getSymbol();
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return;
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case MachineOperand::MO_GlobalAddress:
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O << *Mang->getSymbol(MO.getGlobal());
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break;
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case MachineOperand::MO_BlockAddress: {
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MCSymbol* BA = GetBlockAddressSymbol(MO.getBlockAddress());
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O << BA->getName();
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break;
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}
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case MachineOperand::MO_ExternalSymbol:
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O << *GetExternalSymbolSymbol(MO.getSymbolName());
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break;
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case MachineOperand::MO_JumpTableIndex:
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O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
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<< '_' << MO.getIndex();
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break;
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case MachineOperand::MO_ConstantPoolIndex:
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O << MAI->getPrivateGlobalPrefix() << "CPI"
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<< getFunctionNumber() << "_" << MO.getIndex();
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if (MO.getOffset())
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O << "+" << MO.getOffset();
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break;
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default:
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llvm_unreachable("<unknown operand type>");
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}
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if (closeP) O << ")";
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}
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void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum,
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raw_ostream &O) {
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const MachineOperand &MO = MI->getOperand(opNum);
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if (MO.isImm())
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O << (unsigned short int)MO.getImm();
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else
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printOperand(MI, opNum, O);
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}
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void MipsAsmPrinter::
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printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
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// Load/Store memory operands -- imm($reg)
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// If PIC target the target is loaded as the
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// pattern lw $25,%call16($28)
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printOperand(MI, opNum+1, O);
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O << "(";
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printOperand(MI, opNum, O);
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O << ")";
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}
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void MipsAsmPrinter::
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printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
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// when using stack locations for not load/store instructions
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// print the same way as all normal 3 operand instructions.
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printOperand(MI, opNum, O);
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O << ", ";
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printOperand(MI, opNum+1, O);
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return;
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}
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void MipsAsmPrinter::
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printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
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const char *Modifier) {
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const MachineOperand& MO = MI->getOperand(opNum);
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O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
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}
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void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
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// FIXME: Use SwitchSection.
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// Tell the assembler which ABI we are using
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OutStreamer.EmitRawText("\t.section .mdebug." + Twine(getCurrentABIString()));
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// TODO: handle O64 ABI
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if (Subtarget->isABI_EABI()) {
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if (Subtarget->isGP32bit())
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OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long32"));
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else
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OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long64"));
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}
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// return to previous section
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OutStreamer.EmitRawText(StringRef("\t.previous"));
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}
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MachineLocation
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MipsAsmPrinter::getDebugValueLocation(const MachineInstr *MI) const {
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// Handles frame addresses emitted in MipsInstrInfo::emitFrameIndexDebugValue.
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assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
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assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm() &&
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"Unexpected MachineOperand types");
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return MachineLocation(MI->getOperand(0).getReg(),
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MI->getOperand(1).getImm());
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}
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void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
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raw_ostream &OS) {
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// TODO: implement
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}
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// Force static initialization.
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extern "C" void LLVMInitializeMipsAsmPrinter() {
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RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
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RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);
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RegisterAsmPrinter<MipsAsmPrinter> A(TheMips64Target);
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RegisterAsmPrinter<MipsAsmPrinter> B(TheMips64elTarget);
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}
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