mirror of
https://github.com/c64scene-ar/llvm-6502.git
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b8cab9227a
instead of requiring all "short description" strings to begin with two spaces. This makes these strings less mysterious, and it fixes some cases where short description strings mistakenly did not begin with two spaces. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57521 91177308-0d34-0410-b5e6-96231b3b80d8
335 lines
10 KiB
C++
335 lines
10 KiB
C++
//===-- X86Subtarget.cpp - X86 Subtarget Information ------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the X86 specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#include "X86Subtarget.h"
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#include "X86GenSubtarget.inc"
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#include "llvm/Module.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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static cl::opt<X86Subtarget::AsmWriterFlavorTy>
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AsmWriterFlavor("x86-asm-syntax", cl::init(X86Subtarget::Unset),
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cl::desc("Choose style of code to emit from X86 backend:"),
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cl::values(
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clEnumValN(X86Subtarget::ATT, "att", "Emit AT&T-style assembly"),
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clEnumValN(X86Subtarget::Intel, "intel", "Emit Intel-style assembly"),
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clEnumValEnd));
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/// True if accessing the GV requires an extra load. For Windows, dllimported
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/// symbols are indirect, loading the value at address GV rather then the
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/// value of GV itself. This means that the GlobalAddress must be in the base
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/// or index register of the address, not the GV offset field.
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bool X86Subtarget::GVRequiresExtraLoad(const GlobalValue* GV,
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const TargetMachine& TM,
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bool isDirectCall) const
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{
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// FIXME: PIC
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if (TM.getRelocationModel() != Reloc::Static &&
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TM.getCodeModel() != CodeModel::Large) {
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if (isTargetDarwin()) {
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return (!isDirectCall &&
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(GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
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GV->hasCommonLinkage() ||
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(GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode())));
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} else if (isTargetELF()) {
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// Extra load is needed for all externally visible.
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if (isDirectCall)
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return false;
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if (GV->hasInternalLinkage() || GV->hasHiddenVisibility())
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return false;
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return true;
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} else if (isTargetCygMing() || isTargetWindows()) {
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return (GV->hasDLLImportLinkage());
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}
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}
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return false;
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}
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/// getBZeroEntry - This function returns the name of a function which has an
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/// interface like the non-standard bzero function, if such a function exists on
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/// the current subtarget and it is considered prefereable over memset with zero
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/// passed as the second argument. Otherwise it returns null.
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const char *X86Subtarget::getBZeroEntry() const {
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// Darwin 10 has a __bzero entry point for this purpose.
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if (getDarwinVers() >= 10)
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return "__bzero";
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return 0;
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}
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/// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
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/// specified arguments. If we can't run cpuid on the host, return true.
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bool X86::GetCpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
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unsigned *rECX, unsigned *rEDX) {
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#if defined(__x86_64__)
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// gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
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asm ("movq\t%%rbx, %%rsi\n\t"
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"cpuid\n\t"
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"xchgq\t%%rbx, %%rsi\n\t"
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: "=a" (*rEAX),
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"=S" (*rEBX),
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"=c" (*rECX),
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"=d" (*rEDX)
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: "a" (value));
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return false;
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#elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
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#if defined(__GNUC__)
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asm ("movl\t%%ebx, %%esi\n\t"
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"cpuid\n\t"
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"xchgl\t%%ebx, %%esi\n\t"
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: "=a" (*rEAX),
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"=S" (*rEBX),
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"=c" (*rECX),
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"=d" (*rEDX)
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: "a" (value));
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return false;
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#elif defined(_MSC_VER)
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__asm {
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mov eax,value
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cpuid
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mov esi,rEAX
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mov dword ptr [esi],eax
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mov esi,rEBX
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mov dword ptr [esi],ebx
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mov esi,rECX
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mov dword ptr [esi],ecx
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mov esi,rEDX
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mov dword ptr [esi],edx
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}
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return false;
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#endif
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#endif
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return true;
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}
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void X86Subtarget::AutoDetectSubtargetFeatures() {
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unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
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union {
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unsigned u[3];
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char c[12];
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} text;
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if (X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1))
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return;
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X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
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if ((EDX >> 23) & 0x1) X86SSELevel = MMX;
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if ((EDX >> 25) & 0x1) X86SSELevel = SSE1;
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if ((EDX >> 26) & 0x1) X86SSELevel = SSE2;
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if (ECX & 0x1) X86SSELevel = SSE3;
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if ((ECX >> 9) & 0x1) X86SSELevel = SSSE3;
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if ((ECX >> 19) & 0x1) X86SSELevel = SSE41;
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if ((ECX >> 20) & 0x1) X86SSELevel = SSE42;
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if (memcmp(text.c, "GenuineIntel", 12) == 0 ||
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memcmp(text.c, "AuthenticAMD", 12) == 0) {
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X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
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HasX86_64 = (EDX >> 29) & 0x1;
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}
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}
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static const char *GetCurrentX86CPU() {
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unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
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if (X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
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return "generic";
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unsigned Family = (EAX >> 8) & 0xf; // Bits 8 - 11
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unsigned Model = (EAX >> 4) & 0xf; // Bits 4 - 7
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X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
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bool Em64T = (EDX >> 29) & 0x1;
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union {
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unsigned u[3];
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char c[12];
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} text;
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X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
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if (memcmp(text.c, "GenuineIntel", 12) == 0) {
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switch (Family) {
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case 3:
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return "i386";
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case 4:
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return "i486";
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case 5:
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switch (Model) {
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case 4: return "pentium-mmx";
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default: return "pentium";
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}
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case 6:
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switch (Model) {
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case 1: return "pentiumpro";
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case 3:
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case 5:
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case 6: return "pentium2";
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case 7:
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case 8:
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case 10:
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case 11: return "pentium3";
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case 9:
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case 13: return "pentium-m";
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case 14: return "yonah";
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case 15: return "core2";
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default: return "i686";
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}
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case 15: {
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switch (Model) {
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case 3:
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case 4:
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return (Em64T) ? "nocona" : "prescott";
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default:
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return (Em64T) ? "x86-64" : "pentium4";
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}
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}
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default:
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return "generic";
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}
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} else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
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// FIXME: this poorly matches the generated SubtargetFeatureKV table. There
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// appears to be no way to generate the wide variety of AMD-specific targets
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// from the information returned from CPUID.
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switch (Family) {
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case 4:
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return "i486";
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case 5:
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switch (Model) {
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case 6:
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case 7: return "k6";
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case 8: return "k6-2";
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case 9:
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case 13: return "k6-3";
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default: return "pentium";
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}
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case 6:
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switch (Model) {
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case 4: return "athlon-tbird";
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case 6:
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case 7:
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case 8: return "athlon-mp";
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case 10: return "athlon-xp";
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default: return "athlon";
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}
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case 15:
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switch (Model) {
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case 1: return "opteron";
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case 5: return "athlon-fx"; // also opteron
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default: return "athlon64";
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}
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default:
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return "generic";
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}
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} else {
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return "generic";
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}
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}
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X86Subtarget::X86Subtarget(const Module &M, const std::string &FS, bool is64Bit)
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: AsmFlavor(AsmWriterFlavor)
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, PICStyle(PICStyle::None)
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, X86SSELevel(NoMMXSSE)
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, X863DNowLevel(NoThreeDNow)
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, HasX86_64(false)
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, DarwinVers(0)
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, IsLinux(false)
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, stackAlignment(8)
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// FIXME: this is a known good value for Yonah. How about others?
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, MaxInlineSizeThreshold(128)
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, Is64Bit(is64Bit)
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, TargetType(isELF) { // Default to ELF unless otherwise specified.
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// Determine default and user specified characteristics
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if (!FS.empty()) {
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// If feature string is not empty, parse features string.
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std::string CPU = GetCurrentX86CPU();
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ParseSubtargetFeatures(FS, CPU);
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} else {
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// Otherwise, use CPUID to auto-detect feature set.
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AutoDetectSubtargetFeatures();
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}
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// If requesting codegen for X86-64, make sure that 64-bit and SSE2 features
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// are enabled. These are available on all x86-64 CPUs.
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if (Is64Bit) {
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HasX86_64 = true;
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if (X86SSELevel < SSE2)
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X86SSELevel = SSE2;
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}
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// Set the boolean corresponding to the current target triple, or the default
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// if one cannot be determined, to true.
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const std::string& TT = M.getTargetTriple();
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if (TT.length() > 5) {
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size_t Pos;
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if ((Pos = TT.find("-darwin")) != std::string::npos) {
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TargetType = isDarwin;
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// Compute the darwin version number.
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if (isdigit(TT[Pos+7]))
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DarwinVers = atoi(&TT[Pos+7]);
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else
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DarwinVers = 8; // Minimum supported darwin is Tiger.
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} else if (TT.find("linux") != std::string::npos) {
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// Linux doesn't imply ELF, but we don't currently support anything else.
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TargetType = isELF;
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IsLinux = true;
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} else if (TT.find("cygwin") != std::string::npos) {
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TargetType = isCygwin;
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} else if (TT.find("mingw") != std::string::npos) {
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TargetType = isMingw;
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} else if (TT.find("win32") != std::string::npos) {
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TargetType = isWindows;
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} else if (TT.find("windows") != std::string::npos) {
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TargetType = isWindows;
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}
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} else if (TT.empty()) {
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#if defined(__CYGWIN__)
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TargetType = isCygwin;
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#elif defined(__MINGW32__) || defined(__MINGW64__)
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TargetType = isMingw;
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#elif defined(__APPLE__)
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TargetType = isDarwin;
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#if __APPLE_CC__ > 5400
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DarwinVers = 9; // GCC 5400+ is Leopard.
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#else
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DarwinVers = 8; // Minimum supported darwin is Tiger.
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#endif
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#elif defined(_WIN32) || defined(_WIN64)
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TargetType = isWindows;
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#elif defined(__linux__)
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// Linux doesn't imply ELF, but we don't currently support anything else.
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TargetType = isELF;
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IsLinux = true;
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#endif
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}
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// If the asm syntax hasn't been overridden on the command line, use whatever
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// the target wants.
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if (AsmFlavor == X86Subtarget::Unset) {
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AsmFlavor = (TargetType == isWindows)
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? X86Subtarget::Intel : X86Subtarget::ATT;
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}
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// Stack alignment is 16 bytes on Darwin (both 32 and 64 bit) and for all 64
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// bit targets.
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if (TargetType == isDarwin || Is64Bit)
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stackAlignment = 16;
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if (StackAlignment)
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stackAlignment = StackAlignment;
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}
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