llvm-6502/test/CodeGen
Ekaterina Romanova ed2ca70ccf Fix for http://llvm.org/bugs/show_bug.cgi?id=18590
This patch fixes the bug in peephole optimization that folds a load which defines one vreg into the one and only use of that vreg. With debug info, a DBG_VALUE that referenced the vreg considered to be a use, preventing the optimization. The fix is to ignore DBG_VALUE's during the optimization, and undef a DBG_VALUE that references a vreg that gets removed.
Patch by Trevor Smigiel!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203829 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-13 18:47:12 +00:00
..
AArch64 IR: add a second ordering operand to cmpxhg for failure 2014-03-11 10:48:52 +00:00
ARM Cleanup: Remove use of old "-enable-correct-eh-support" option from a test 2014-03-13 16:23:00 +00:00
CPP
Generic
Hexagon
Inputs
Mips [mips] BSEL's and BINS[RL] operands are reversed compared to the vselect node used in the pattern. 2014-03-12 11:54:00 +00:00
MSP430
NVPTX
PowerPC [PowerPC] Initial support for the VSX instruction set 2014-03-13 07:58:58 +00:00
R600 R600: LDS instructions shouldn't implicitly define OQAP 2014-03-13 17:13:04 +00:00
SPARC IR: add a second ordering operand to cmpxhg for failure 2014-03-11 10:48:52 +00:00
SystemZ IR: add a second ordering operand to cmpxhg for failure 2014-03-11 10:48:52 +00:00
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X86 Fix for http://llvm.org/bugs/show_bug.cgi?id=18590 2014-03-13 18:47:12 +00:00
XCore