llvm-6502/test/CodeGen/X86/fast-isel-divrem-x86-64.ll
Eli Bendersky 50125482d3 This patch teaches x86 fast-isel to generate the native div/idiv instructions
for the sdiv/srem/udiv/urem bitcode instructions.  This is done for the i8,
i16, and i32 types, as well as i64 for the x86_64 target.

Patch by Jim Stichnoth



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179715 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-17 20:10:13 +00:00

42 lines
824 B
LLVM

; RUN: llc -mtriple=x86_64-none-linux -fast-isel -fast-isel-abort < %s | FileCheck %s
define i64 @test_sdiv64(i64 %dividend, i64 %divisor) nounwind {
entry:
%result = sdiv i64 %dividend, %divisor
ret i64 %result
}
; CHECK: test_sdiv64:
; CHECK: cqto
; CHECK: idivq
define i64 @test_srem64(i64 %dividend, i64 %divisor) nounwind {
entry:
%result = srem i64 %dividend, %divisor
ret i64 %result
}
; CHECK: test_srem64:
; CHECK: cqto
; CHECK: idivq
define i64 @test_udiv64(i64 %dividend, i64 %divisor) nounwind {
entry:
%result = udiv i64 %dividend, %divisor
ret i64 %result
}
; CHECK: test_udiv64:
; CHECK: xorl
; CHECK: divq
define i64 @test_urem64(i64 %dividend, i64 %divisor) nounwind {
entry:
%result = urem i64 %dividend, %divisor
ret i64 %result
}
; CHECK: test_urem64:
; CHECK: xorl
; CHECK: divq