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https://github.com/c64scene-ar/llvm-6502.git
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8a8d479214
change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145714 91177308-0d34-0410-b5e6-96231b3b80d8
100 lines
3.3 KiB
C++
100 lines
3.3 KiB
C++
//===-- PPCTargetMachine.h - Define TargetMachine for PowerPC -----*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the PowerPC specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef PPC_TARGETMACHINE_H
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#define PPC_TARGETMACHINE_H
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#include "PPCFrameLowering.h"
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#include "PPCSubtarget.h"
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#include "PPCJITInfo.h"
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#include "PPCInstrInfo.h"
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#include "PPCISelLowering.h"
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#include "PPCSelectionDAGInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetData.h"
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namespace llvm {
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class PassManager;
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class GlobalValue;
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/// PPCTargetMachine - Common code between 32-bit and 64-bit PowerPC targets.
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///
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class PPCTargetMachine : public LLVMTargetMachine {
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PPCSubtarget Subtarget;
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const TargetData DataLayout; // Calculates type size & alignment
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PPCInstrInfo InstrInfo;
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PPCFrameLowering FrameLowering;
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PPCJITInfo JITInfo;
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PPCTargetLowering TLInfo;
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PPCSelectionDAGInfo TSInfo;
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InstrItineraryData InstrItins;
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public:
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PPCTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL, bool is64Bit);
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virtual const PPCInstrInfo *getInstrInfo() const { return &InstrInfo; }
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virtual const PPCFrameLowering *getFrameLowering() const {
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return &FrameLowering;
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}
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virtual PPCJITInfo *getJITInfo() { return &JITInfo; }
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virtual const PPCTargetLowering *getTargetLowering() const {
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return &TLInfo;
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}
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virtual const PPCSelectionDAGInfo* getSelectionDAGInfo() const {
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return &TSInfo;
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}
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virtual const PPCRegisterInfo *getRegisterInfo() const {
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return &InstrInfo.getRegisterInfo();
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}
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virtual const TargetData *getTargetData() const { return &DataLayout; }
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virtual const PPCSubtarget *getSubtargetImpl() const { return &Subtarget; }
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virtual const InstrItineraryData *getInstrItineraryData() const {
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return &InstrItins;
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}
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// Pass Pipeline Configuration
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virtual bool addInstSelector(PassManagerBase &PM);
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virtual bool addPreEmitPass(PassManagerBase &PM);
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virtual bool addCodeEmitter(PassManagerBase &PM,
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JITCodeEmitter &JCE);
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virtual bool getEnableTailMergeDefault() const;
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};
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/// PPC32TargetMachine - PowerPC 32-bit target machine.
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///
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class PPC32TargetMachine : public PPCTargetMachine {
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public:
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PPC32TargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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};
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/// PPC64TargetMachine - PowerPC 64-bit target machine.
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///
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class PPC64TargetMachine : public PPCTargetMachine {
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public:
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PPC64TargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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};
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} // end namespace llvm
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#endif
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