llvm-6502/test/CodeGen
Ulrich Weigand f0ef882828 [PowerPC] Report true displacement value from getPreIndexedAddressParts
DAGCombiner::CombineToPreIndexedLoadStore calls a target routine to
decompose a memory address into a base/offset pair.  It expects the
offset (if constant) to be the true displacement value in order to
perform optional additional optimizations; in particular, to convert
other uses of the original pointer into uses of the new base pointer
after pre-increment.

The PowerPC implementation of getPreIndexedAddressParts, however,
simply calls SelectAddressRegImm, which returns a TargetConstant.
This value is appropriate for encoding into the instruction, but
it is not always usable as true displacement value:

- Its type is always MVT::i32, even on 64-bit, where addresses
  ought to be i64 ... this causes the optimization to simply
  always fail on 64-bit due to this line in DAGCombiner:

      // FIXME: In some cases, we can be smarter about this.
      if (Op1.getValueType() != Offset.getValueType()) {

- Its value is truncated to an unsigned 16-bit value if negative.
  This causes the above opimization to generate wrong code.

This patch fixes both problems by simply returning the true
displacement value (in its original type).  This doesn't
affect any other user of the displacement.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182012 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16 14:53:05 +00:00
..
AArch64 AArch64: support literal pool access in large memory model. 2013-05-04 16:54:07 +00:00
ARM ARM ISel: Don't create illegal types during LowerMUL 2013-05-14 22:33:24 +00:00
CPP
Generic TBAA: remove !tbaa from testing cases if not used. 2013-04-30 17:52:57 +00:00
Hexagon Hexagon: Pass to replace tranfer/copy instructions into combine instruction 2013-05-14 18:54:06 +00:00
Inputs
MBlaze
Mips Add more addFrameMove test coverage. 2013-05-16 14:51:26 +00:00
MSP430 DAGCombiner: Simplify inverted bit tests 2013-05-08 06:44:42 +00:00
NVPTX [NVPTX] Remove support for SM < 2.0. This was never fully supported anyway. 2013-03-30 14:29:30 +00:00
PowerPC [PowerPC] Report true displacement value from getPreIndexedAddressParts 2013-05-16 14:53:05 +00:00
R600 R600/SI: Add lit test coverage for the remaining patterns added recently 2013-05-14 09:53:30 +00:00
SI
SPARC Recognize sparc64 as an alias for sparcv9 triples. 2013-05-14 17:47:27 +00:00
SystemZ [SystemZ] Make use of SUBTRACT HALFWORD 2013-05-15 15:05:29 +00:00
Thumb LocalStackSlotAllocation improvements 2013-04-30 20:04:37 +00:00
Thumb2 Fix ARM FastISel tests, as a first step to enabling ARM FastISel 2013-05-14 16:26:38 +00:00
X86 Relax CHECK-NEXTs a bit to cope with atom's return nop padding. 2013-05-16 11:46:50 +00:00
XCore [XCore] Fix handling of functions where only the LR is spilled. 2013-05-09 16:43:42 +00:00