Andrea Di Biagio f0f66a254d [X86] When commuting SSE immediate blend, make sure that the new blend mask is a valid imm8. ... Example: define <4 x i32> @test(<4 x i32> %a, <4 x i32> %b) { %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 5, i32 6, i32 3> ret <4 x i32> %shuffle } Before llc (-mattr=+sse4.1), produced the following assembly instruction: pblendw $4294967103, %xmm1, %xmm0 After pblendw $63, %xmm1, %xmm0 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221455 91177308-0d34-0410-b5e6-96231b3b80d8		2014-11-06 14:36:45 +00:00
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AArch64	[AArch64] Use the correct register class for ORR.	2014-11-04 22:20:07 +00:00
ARM	ARM: try to add extra CS-register whenever stack alignment >= 8.	2014-11-05 00:27:20 +00:00
CPP
Generic
Hexagon
Inputs
Mips	[mips] Tolerate the use of the %z inline asm operand modifier with non-immediates.	2014-11-06 14:25:42 +00:00
MSP430
NVPTX	[NVPTX] Add NVPTXLowerStructArgs pass	2014-11-05 18:19:30 +00:00
PowerPC
R600	R600/SI: Add testcase I forgot to commit from months ago	2014-11-05 19:01:22 +00:00
SPARC
SystemZ
Thumb	Improve logic that decides if its profitable to commute when some of the virtual registers involved have uses/defs chains connecting them to physical register. Fix up the tests that this change improves.	2014-11-05 06:43:02 +00:00
Thumb2
X86	[X86] When commuting SSE immediate blend, make sure that the new blend mask is a valid imm8.	2014-11-06 14:36:45 +00:00
XCore