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non-debug build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29105 91177308-0d34-0410-b5e6-96231b3b80d8
518 lines
18 KiB
C++
518 lines
18 KiB
C++
//===-- AlphaISelDAGToDAG.cpp - Alpha pattern matching inst selector ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Andrew Lenharth and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a pattern matching instruction selector for Alpha,
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// converting from a legalized dag to a Alpha dag.
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//
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//===----------------------------------------------------------------------===//
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#include "Alpha.h"
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#include "AlphaTargetMachine.h"
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#include "AlphaISelLowering.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Constants.h"
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#include "llvm/GlobalValue.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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#include <algorithm>
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#include <iostream>
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#include <set>
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using namespace llvm;
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namespace {
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//===--------------------------------------------------------------------===//
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/// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
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/// instructions for SelectionDAG operations.
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class AlphaDAGToDAGISel : public SelectionDAGISel {
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AlphaTargetLowering AlphaLowering;
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static const int64_t IMM_LOW = -32768;
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static const int64_t IMM_HIGH = 32767;
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static const int64_t IMM_MULT = 65536;
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static const int64_t IMM_FULLHIGH = IMM_HIGH + IMM_HIGH * IMM_MULT;
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static const int64_t IMM_FULLLOW = IMM_LOW + IMM_LOW * IMM_MULT;
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static int64_t get_ldah16(int64_t x) {
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int64_t y = x / IMM_MULT;
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if (x % IMM_MULT > IMM_HIGH)
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++y;
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return y;
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}
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static int64_t get_lda16(int64_t x) {
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return x - get_ldah16(x) * IMM_MULT;
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}
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static uint64_t get_zapImm(uint64_t x) {
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unsigned int build = 0;
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for(int i = 0; i < 8; ++i)
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{
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if ((x & 0x00FF) == 0x00FF)
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build |= 1 << i;
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else if ((x & 0x00FF) != 0)
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{ build = 0; break; }
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x >>= 8;
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}
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return build;
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}
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static uint64_t getNearPower2(uint64_t x) {
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if (!x) return 0;
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unsigned at = CountLeadingZeros_64(x);
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uint64_t complow = 1 << (63 - at);
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uint64_t comphigh = 1 << (64 - at);
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//std::cerr << x << ":" << complow << ":" << comphigh << "\n";
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if (abs(complow - x) <= abs(comphigh - x))
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return complow;
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else
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return comphigh;
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}
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static bool isFPZ(SDOperand N) {
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ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
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return (CN && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)));
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}
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static bool isFPZn(SDOperand N) {
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ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
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return (CN && CN->isExactlyValue(-0.0));
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}
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static bool isFPZp(SDOperand N) {
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ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
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return (CN && CN->isExactlyValue(+0.0));
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}
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public:
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AlphaDAGToDAGISel(TargetMachine &TM)
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: SelectionDAGISel(AlphaLowering), AlphaLowering(TM)
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{}
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/// getI64Imm - Return a target constant with the specified value, of type
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/// i64.
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inline SDOperand getI64Imm(int64_t Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i64);
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}
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// Select - Convert the specified operand from a target-independent to a
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// target-specific node if it hasn't already been changed.
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void Select(SDOperand &Result, SDOperand Op);
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
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virtual const char *getPassName() const {
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return "Alpha DAG->DAG Pattern Instruction Selection";
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}
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/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
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/// inline asm expressions.
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virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
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char ConstraintCode,
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std::vector<SDOperand> &OutOps,
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SelectionDAG &DAG) {
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SDOperand Op0;
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switch (ConstraintCode) {
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default: return true;
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case 'm': // memory
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Select(Op0, Op);
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break;
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}
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OutOps.push_back(Op0);
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return false;
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}
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// Include the pieces autogenerated from the target description.
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#include "AlphaGenDAGISel.inc"
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private:
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SDOperand getGlobalBaseReg();
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SDOperand getGlobalRetAddr();
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SDOperand SelectCALL(SDOperand Op);
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};
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}
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/// getGlobalBaseReg - Output the instructions required to put the
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/// GOT address into a register.
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///
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SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
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return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
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AlphaLowering.getVRegGP(),
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MVT::i64);
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}
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/// getRASaveReg - Grab the return address
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///
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SDOperand AlphaDAGToDAGISel::getGlobalRetAddr() {
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return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
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AlphaLowering.getVRegRA(),
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MVT::i64);
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}
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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void AlphaDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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DEBUG(BB->dump());
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// Select target instructions for the DAG.
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DAG.setRoot(SelectRoot(DAG.getRoot()));
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assert(InFlightSet.empty() && "ISel InFlightSet has not been emptied!");
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CodeGenMap.clear();
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HandleMap.clear();
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ReplaceMap.clear();
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DAG.RemoveDeadNodes();
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// Emit machine code to BB.
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ScheduleAndEmitDAG(DAG);
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}
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// Select - Convert the specified operand from a target-independent to a
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// target-specific node if it hasn't already been changed.
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void AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
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SDNode *N = Op.Val;
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if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
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N->getOpcode() < AlphaISD::FIRST_NUMBER) {
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Result = Op;
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return; // Already selected.
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}
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// If this has already been converted, use it.
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std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
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if (CGMI != CodeGenMap.end()) {
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Result = CGMI->second;
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return;
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}
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switch (N->getOpcode()) {
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default: break;
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case AlphaISD::CALL:
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Result = SelectCALL(Op);
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return;
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case ISD::FrameIndex: {
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int FI = cast<FrameIndexSDNode>(N)->getIndex();
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Result = CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
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CurDAG->getTargetFrameIndex(FI, MVT::i32),
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getI64Imm(0));
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return;
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}
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case AlphaISD::GlobalBaseReg:
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Result = getGlobalBaseReg();
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return;
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case AlphaISD::GlobalRetAddr:
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Result = getGlobalRetAddr();
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return;
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case AlphaISD::DivCall: {
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SDOperand Chain = CurDAG->getEntryNode();
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SDOperand N0, N1, N2;
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Select(N0, Op.getOperand(0));
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Select(N1, Op.getOperand(1));
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Select(N2, Op.getOperand(2));
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Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, N1,
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SDOperand(0,0));
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Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, N2,
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Chain.getValue(1));
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Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, N0,
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Chain.getValue(1));
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SDNode *CNode =
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CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag,
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Chain, Chain.getValue(1));
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Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64,
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SDOperand(CNode, 1));
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Result = CurDAG->SelectNodeTo(N, Alpha::BIS, MVT::i64, Chain, Chain);
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return;
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}
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case ISD::READCYCLECOUNTER: {
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SDOperand Chain;
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Select(Chain, N->getOperand(0)); //Select chain
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Result = CurDAG->SelectNodeTo(N, Alpha::RPCC, MVT::i64, Chain);
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return;
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}
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case ISD::Constant: {
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uint64_t uval = cast<ConstantSDNode>(N)->getValue();
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if (uval == 0) {
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Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), Alpha::R31,
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MVT::i64);
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return;
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}
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int64_t val = (int64_t)uval;
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int32_t val32 = (int32_t)val;
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if (val <= IMM_HIGH + IMM_HIGH * IMM_MULT &&
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val >= IMM_LOW + IMM_LOW * IMM_MULT)
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break; //(LDAH (LDA))
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if ((uval >> 32) == 0 && //empty upper bits
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val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT)
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// val32 >= IMM_LOW + IMM_LOW * IMM_MULT) //always true
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break; //(zext (LDAH (LDA)))
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//Else use the constant pool
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MachineConstantPool *CP = BB->getParent()->getConstantPool();
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ConstantUInt *C =
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ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , uval);
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SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
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SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI,
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getGlobalBaseReg());
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Result = CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
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CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode());
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return;
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}
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case ISD::TargetConstantFP: {
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ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
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bool isDouble = N->getValueType(0) == MVT::f64;
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MVT::ValueType T = isDouble ? MVT::f64 : MVT::f32;
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if (CN->isExactlyValue(+0.0)) {
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Result = CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
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T, CurDAG->getRegister(Alpha::F31, T),
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CurDAG->getRegister(Alpha::F31, T));
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return;
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} else if ( CN->isExactlyValue(-0.0)) {
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Result = CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
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T, CurDAG->getRegister(Alpha::F31, T),
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CurDAG->getRegister(Alpha::F31, T));
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return;
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} else {
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abort();
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}
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break;
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}
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case ISD::SETCC:
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if (MVT::isFloatingPoint(N->getOperand(0).Val->getValueType(0))) {
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unsigned Opc = Alpha::WTF;
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ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
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bool rev = false;
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bool isNE = false;
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switch(CC) {
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default: DEBUG(N->dump()); assert(0 && "Unknown FP comparison!");
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case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ: Opc = Alpha::CMPTEQ; break;
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case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT: Opc = Alpha::CMPTLT; break;
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case ISD::SETLE: case ISD::SETOLE: case ISD::SETULE: Opc = Alpha::CMPTLE; break;
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case ISD::SETGT: case ISD::SETOGT: case ISD::SETUGT: Opc = Alpha::CMPTLT; rev = true; break;
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case ISD::SETGE: case ISD::SETOGE: case ISD::SETUGE: Opc = Alpha::CMPTLE; rev = true; break;
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case ISD::SETNE: case ISD::SETONE: case ISD::SETUNE: Opc = Alpha::CMPTEQ; isNE = true; break;
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};
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SDOperand tmp1, tmp2;
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Select(tmp1, N->getOperand(0));
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Select(tmp2, N->getOperand(1));
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SDNode *cmp = CurDAG->getTargetNode(Opc, MVT::f64,
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rev?tmp2:tmp1,
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rev?tmp1:tmp2);
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if (isNE)
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cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, SDOperand(cmp, 0),
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CurDAG->getRegister(Alpha::F31, MVT::f64));
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SDOperand LD;
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if (AlphaLowering.hasITOF()) {
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LD = CurDAG->getNode(AlphaISD::FTOIT_, MVT::i64, SDOperand(cmp, 0));
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} else {
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int FrameIdx =
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CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
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SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
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SDOperand ST =
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SDOperand(CurDAG->getTargetNode(Alpha::STT, MVT::Other,
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SDOperand(cmp, 0), FI,
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CurDAG->getRegister(Alpha::R31, MVT::i64)), 0);
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LD = SDOperand(CurDAG->getTargetNode(Alpha::LDQ, MVT::i64, FI,
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CurDAG->getRegister(Alpha::R31, MVT::i64),
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ST), 0);
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}
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Result = SDOperand(CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64,
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CurDAG->getRegister(Alpha::R31, MVT::i64),
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LD), 0);
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return;
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}
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break;
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case ISD::SELECT:
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if (MVT::isFloatingPoint(N->getValueType(0)) &&
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(N->getOperand(0).getOpcode() != ISD::SETCC ||
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!MVT::isFloatingPoint(N->getOperand(0).getOperand(1).getValueType()))) {
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//This should be the condition not covered by the Patterns
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//FIXME: Don't have SelectCode die, but rather return something testable
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// so that things like this can be caught in fall though code
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//move int to fp
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bool isDouble = N->getValueType(0) == MVT::f64;
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SDOperand LD, cond, TV, FV;
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Select(cond, N->getOperand(0));
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Select(TV, N->getOperand(1));
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Select(FV, N->getOperand(2));
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if (AlphaLowering.hasITOF()) {
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LD = CurDAG->getNode(AlphaISD::ITOFT_, MVT::f64, cond);
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} else {
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int FrameIdx =
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CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
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SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
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SDOperand ST =
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SDOperand(CurDAG->getTargetNode(Alpha::STQ, MVT::Other,
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cond, FI, CurDAG->getRegister(Alpha::R31, MVT::i64)), 0);
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LD = SDOperand(CurDAG->getTargetNode(Alpha::LDT, MVT::f64, FI,
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CurDAG->getRegister(Alpha::R31, MVT::i64),
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ST), 0);
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}
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Result = SDOperand(CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES,
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MVT::f64, FV, TV, LD), 0);
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return;
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}
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break;
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case ISD::AND: {
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ConstantSDNode* SC = NULL;
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ConstantSDNode* MC = NULL;
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if (N->getOperand(0).getOpcode() == ISD::SRL &&
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(MC = dyn_cast<ConstantSDNode>(N->getOperand(1))) &&
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(SC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1))))
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{
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uint64_t sval = SC->getValue();
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uint64_t mval = MC->getValue();
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if (get_zapImm(mval)) //the result is a zap, let the autogened stuff deal
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break;
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// given mask X, and shift S, we want to see if there is any zap in the mask
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// if we play around with the botton S bits
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uint64_t dontcare = (~0ULL) >> (64 - sval);
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uint64_t mask = mval << sval;
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if (get_zapImm(mask | dontcare))
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mask = mask | dontcare;
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if (get_zapImm(mask)) {
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SDOperand Src;
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Select(Src, N->getOperand(0).getOperand(0));
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SDOperand Z =
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SDOperand(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64, Src,
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getI64Imm(get_zapImm(mask))), 0);
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Result = SDOperand(CurDAG->getTargetNode(Alpha::SRL, MVT::i64, Z,
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getI64Imm(sval)), 0);
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return;
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}
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}
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break;
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}
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}
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SelectCode(Result, Op);
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}
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SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
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//TODO: add flag stuff to prevent nondeturministic breakage!
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SDNode *N = Op.Val;
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SDOperand Chain;
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SDOperand Addr = N->getOperand(1);
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SDOperand InFlag(0,0); // Null incoming flag value.
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Select(Chain, N->getOperand(0));
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std::vector<SDOperand> CallOperands;
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std::vector<MVT::ValueType> TypeOperands;
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//grab the arguments
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for(int i = 2, e = N->getNumOperands(); i < e; ++i) {
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SDOperand Tmp;
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TypeOperands.push_back(N->getOperand(i).getValueType());
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Select(Tmp, N->getOperand(i));
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CallOperands.push_back(Tmp);
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}
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int count = N->getNumOperands() - 2;
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static const unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
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Alpha::R19, Alpha::R20, Alpha::R21};
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static const unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
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Alpha::F19, Alpha::F20, Alpha::F21};
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for (int i = 6; i < count; ++i) {
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unsigned Opc = Alpha::WTF;
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|
if (MVT::isInteger(TypeOperands[i])) {
|
|
Opc = Alpha::STQ;
|
|
} else if (TypeOperands[i] == MVT::f32) {
|
|
Opc = Alpha::STS;
|
|
} else if (TypeOperands[i] == MVT::f64) {
|
|
Opc = Alpha::STT;
|
|
} else
|
|
assert(0 && "Unknown operand");
|
|
Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, CallOperands[i],
|
|
getI64Imm((i - 6) * 8),
|
|
CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64),
|
|
Chain), 0);
|
|
}
|
|
for (int i = 0; i < std::min(6, count); ++i) {
|
|
if (MVT::isInteger(TypeOperands[i])) {
|
|
Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i], InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
} else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) {
|
|
Chain = CurDAG->getCopyToReg(Chain, args_float[i], CallOperands[i], InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
} else
|
|
assert(0 && "Unknown operand");
|
|
}
|
|
|
|
// Finally, once everything is in registers to pass to the call, emit the
|
|
// call itself.
|
|
if (Addr.getOpcode() == AlphaISD::GPRelLo) {
|
|
SDOperand GOT = getGlobalBaseReg();
|
|
Chain = CurDAG->getCopyToReg(Chain, Alpha::R29, GOT, InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
Chain = SDOperand(CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag,
|
|
Addr.getOperand(0), Chain, InFlag), 0);
|
|
} else {
|
|
Select(Addr, Addr);
|
|
Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
Chain = SDOperand(CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag,
|
|
Chain, InFlag), 0);
|
|
}
|
|
InFlag = Chain.getValue(1);
|
|
|
|
std::vector<SDOperand> CallResults;
|
|
|
|
switch (N->getValueType(0)) {
|
|
default: assert(0 && "Unexpected ret value!");
|
|
case MVT::Other: break;
|
|
case MVT::i64:
|
|
Chain = CurDAG->getCopyFromReg(Chain, Alpha::R0, MVT::i64, InFlag).getValue(1);
|
|
CallResults.push_back(Chain.getValue(0));
|
|
break;
|
|
case MVT::f32:
|
|
Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f32, InFlag).getValue(1);
|
|
CallResults.push_back(Chain.getValue(0));
|
|
break;
|
|
case MVT::f64:
|
|
Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f64, InFlag).getValue(1);
|
|
CallResults.push_back(Chain.getValue(0));
|
|
break;
|
|
}
|
|
|
|
CallResults.push_back(Chain);
|
|
for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
|
|
CodeGenMap[Op.getValue(i)] = CallResults[i];
|
|
return CallResults[Op.ResNo];
|
|
}
|
|
|
|
|
|
/// createAlphaISelDag - This pass converts a legalized DAG into a
|
|
/// Alpha-specific DAG, ready for instruction scheduling.
|
|
///
|
|
FunctionPass *llvm::createAlphaISelDag(TargetMachine &TM) {
|
|
return new AlphaDAGToDAGISel(TM);
|
|
}
|