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working. The instruction selector changes will hopefully be coming later this week once they are debugged. This is necessary to support the darwin x86 FP model, and is recommended by intel as the replacement for x87. As a bonus, the register allocator knows how to deal with these registers across basic blocks, unliky the FP stackifier. This leads to significantly better codegen in several cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22300 91177308-0d34-0410-b5e6-96231b3b80d8 |
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.. | ||
Alpha | ||
CBackend | ||
IA64 | ||
PowerPC | ||
Skeleton | ||
Sparc | ||
SparcV8 | ||
SparcV9 | ||
X86 | ||
Makefile | ||
MRegisterInfo.cpp | ||
Target.td | ||
TargetData.cpp | ||
TargetFrameInfo.cpp | ||
TargetInstrInfo.cpp | ||
TargetMachine.cpp | ||
TargetMachineRegistry.cpp | ||
TargetSchedInfo.cpp |