mirror of
https://github.com/c64scene-ar/llvm-6502.git
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f28987b76e
This simplifies many of the target description files since it is common for register classes to be related or contain sequences of numbered registers. I have verified that this doesn't change the files generated by TableGen for ARM and X86. It alters the allocation order of MBlaze GPR and Mips FGR32 registers, but I believe the change is benign. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133105 91177308-0d34-0410-b5e6-96231b3b80d8
200 lines
7.0 KiB
TableGen
200 lines
7.0 KiB
TableGen
//===- SystemZRegisterInfo.td - The PowerPC Register File ------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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class SystemZReg<string n> : Register<n> {
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let Namespace = "SystemZ";
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}
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class SystemZRegWithSubregs<string n, list<Register> subregs>
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: RegisterWithSubRegs<n, subregs> {
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let Namespace = "SystemZ";
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}
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// We identify all our registers with a 4-bit ID, for consistency's sake.
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// GPR32 - Lower 32 bits of one of the 16 64-bit general-purpose registers
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class GPR32<bits<4> num, string n> : SystemZReg<n> {
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field bits<4> Num = num;
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}
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// GPR64 - One of the 16 64-bit general-purpose registers
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class GPR64<bits<4> num, string n, list<Register> subregs,
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list<Register> aliases = []>
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: SystemZRegWithSubregs<n, subregs> {
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field bits<4> Num = num;
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let Aliases = aliases;
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}
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// GPR128 - 8 even-odd register pairs
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class GPR128<bits<4> num, string n, list<Register> subregs,
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list<Register> aliases = []>
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: SystemZRegWithSubregs<n, subregs> {
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field bits<4> Num = num;
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let Aliases = aliases;
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}
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// FPRS - Lower 32 bits of one of the 16 64-bit floating-point registers
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class FPRS<bits<4> num, string n> : SystemZReg<n> {
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field bits<4> Num = num;
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}
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// FPRL - One of the 16 64-bit floating-point registers
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class FPRL<bits<4> num, string n, list<Register> subregs>
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: SystemZRegWithSubregs<n, subregs> {
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field bits<4> Num = num;
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}
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let Namespace = "SystemZ" in {
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def subreg_32bit : SubRegIndex;
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def subreg_odd32 : SubRegIndex;
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def subreg_even : SubRegIndex;
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def subreg_odd : SubRegIndex;
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}
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// General-purpose registers
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def R0W : GPR32< 0, "r0">;
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def R1W : GPR32< 1, "r1">;
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def R2W : GPR32< 2, "r2">;
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def R3W : GPR32< 3, "r3">;
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def R4W : GPR32< 4, "r4">;
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def R5W : GPR32< 5, "r5">;
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def R6W : GPR32< 6, "r6">;
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def R7W : GPR32< 7, "r7">;
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def R8W : GPR32< 8, "r8">;
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def R9W : GPR32< 9, "r9">;
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def R10W : GPR32<10, "r10">;
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def R11W : GPR32<11, "r11">;
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def R12W : GPR32<12, "r12">;
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def R13W : GPR32<13, "r13">;
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def R14W : GPR32<14, "r14">;
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def R15W : GPR32<15, "r15">;
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let SubRegIndices = [subreg_32bit] in {
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def R0D : GPR64< 0, "r0", [R0W]>, DwarfRegNum<[0]>;
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def R1D : GPR64< 1, "r1", [R1W]>, DwarfRegNum<[1]>;
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def R2D : GPR64< 2, "r2", [R2W]>, DwarfRegNum<[2]>;
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def R3D : GPR64< 3, "r3", [R3W]>, DwarfRegNum<[3]>;
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def R4D : GPR64< 4, "r4", [R4W]>, DwarfRegNum<[4]>;
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def R5D : GPR64< 5, "r5", [R5W]>, DwarfRegNum<[5]>;
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def R6D : GPR64< 6, "r6", [R6W]>, DwarfRegNum<[6]>;
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def R7D : GPR64< 7, "r7", [R7W]>, DwarfRegNum<[7]>;
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def R8D : GPR64< 8, "r8", [R8W]>, DwarfRegNum<[8]>;
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def R9D : GPR64< 9, "r9", [R9W]>, DwarfRegNum<[9]>;
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def R10D : GPR64<10, "r10", [R10W]>, DwarfRegNum<[10]>;
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def R11D : GPR64<11, "r11", [R11W]>, DwarfRegNum<[11]>;
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def R12D : GPR64<12, "r12", [R12W]>, DwarfRegNum<[12]>;
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def R13D : GPR64<13, "r13", [R13W]>, DwarfRegNum<[13]>;
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def R14D : GPR64<14, "r14", [R14W]>, DwarfRegNum<[14]>;
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def R15D : GPR64<15, "r15", [R15W]>, DwarfRegNum<[15]>;
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}
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// Register pairs
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let SubRegIndices = [subreg_32bit, subreg_odd32] in {
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def R0P : GPR64< 0, "r0", [R0W, R1W], [R0D, R1D]>;
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def R2P : GPR64< 2, "r2", [R2W, R3W], [R2D, R3D]>;
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def R4P : GPR64< 4, "r4", [R4W, R5W], [R4D, R5D]>;
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def R6P : GPR64< 6, "r6", [R6W, R7W], [R6D, R7D]>;
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def R8P : GPR64< 8, "r8", [R8W, R9W], [R8D, R9D]>;
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def R10P : GPR64<10, "r10", [R10W, R11W], [R10D, R11D]>;
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def R12P : GPR64<12, "r12", [R12W, R13W], [R12D, R13D]>;
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def R14P : GPR64<14, "r14", [R14W, R15W], [R14D, R15D]>;
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}
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let SubRegIndices = [subreg_even, subreg_odd],
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CompositeIndices = [(subreg_odd32 subreg_odd, subreg_32bit)] in {
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def R0Q : GPR128< 0, "r0", [R0D, R1D], [R0P]>;
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def R2Q : GPR128< 2, "r2", [R2D, R3D], [R2P]>;
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def R4Q : GPR128< 4, "r4", [R4D, R5D], [R4P]>;
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def R6Q : GPR128< 6, "r6", [R6D, R7D], [R6P]>;
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def R8Q : GPR128< 8, "r8", [R8D, R9D], [R8P]>;
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def R10Q : GPR128<10, "r10", [R10D, R11D], [R10P]>;
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def R12Q : GPR128<12, "r12", [R12D, R13D], [R12P]>;
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def R14Q : GPR128<14, "r14", [R14D, R15D], [R14P]>;
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}
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// Floating-point registers
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def F0S : FPRS< 0, "f0">, DwarfRegNum<[16]>;
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def F1S : FPRS< 1, "f1">, DwarfRegNum<[17]>;
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def F2S : FPRS< 2, "f2">, DwarfRegNum<[18]>;
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def F3S : FPRS< 3, "f3">, DwarfRegNum<[19]>;
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def F4S : FPRS< 4, "f4">, DwarfRegNum<[20]>;
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def F5S : FPRS< 5, "f5">, DwarfRegNum<[21]>;
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def F6S : FPRS< 6, "f6">, DwarfRegNum<[22]>;
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def F7S : FPRS< 7, "f7">, DwarfRegNum<[23]>;
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def F8S : FPRS< 8, "f8">, DwarfRegNum<[24]>;
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def F9S : FPRS< 9, "f9">, DwarfRegNum<[25]>;
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def F10S : FPRS<10, "f10">, DwarfRegNum<[26]>;
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def F11S : FPRS<11, "f11">, DwarfRegNum<[27]>;
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def F12S : FPRS<12, "f12">, DwarfRegNum<[28]>;
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def F13S : FPRS<13, "f13">, DwarfRegNum<[29]>;
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def F14S : FPRS<14, "f14">, DwarfRegNum<[30]>;
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def F15S : FPRS<15, "f15">, DwarfRegNum<[31]>;
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let SubRegIndices = [subreg_32bit] in {
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def F0L : FPRL< 0, "f0", [F0S]>;
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def F1L : FPRL< 1, "f1", [F1S]>;
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def F2L : FPRL< 2, "f2", [F2S]>;
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def F3L : FPRL< 3, "f3", [F3S]>;
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def F4L : FPRL< 4, "f4", [F4S]>;
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def F5L : FPRL< 5, "f5", [F5S]>;
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def F6L : FPRL< 6, "f6", [F6S]>;
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def F7L : FPRL< 7, "f7", [F7S]>;
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def F8L : FPRL< 8, "f8", [F8S]>;
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def F9L : FPRL< 9, "f9", [F9S]>;
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def F10L : FPRL<10, "f10", [F10S]>;
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def F11L : FPRL<11, "f11", [F11S]>;
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def F12L : FPRL<12, "f12", [F12S]>;
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def F13L : FPRL<13, "f13", [F13S]>;
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def F14L : FPRL<14, "f14", [F14S]>;
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def F15L : FPRL<15, "f15", [F15S]>;
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}
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// Status register
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def PSW : SystemZReg<"psw">;
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/// Register classes
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def GR32 : RegisterClass<"SystemZ", [i32], 32, (sequence "R%uW", 0, 15)>;
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/// Registers used to generate address. Everything except R0.
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def ADDR32 : RegisterClass<"SystemZ", [i32], 32, (sub GR32, R0W)>;
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def GR64 : RegisterClass<"SystemZ", [i64], 64, (sequence "R%uD", 0, 15)> {
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let SubRegClasses = [(GR32 subreg_32bit)];
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}
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def ADDR64 : RegisterClass<"SystemZ", [i64], 64, (sub GR64, R0D)> {
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let SubRegClasses = [(ADDR32 subreg_32bit)];
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}
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// Even-odd register pairs
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def GR64P : RegisterClass<"SystemZ", [v2i32], 64, (add R0P, R2P, R4P, R6P, R8P,
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R10P, R12P, R14P)> {
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let SubRegClasses = [(GR32 subreg_32bit, subreg_odd32)];
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}
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def GR128 : RegisterClass<"SystemZ", [v2i64], 128, (add R0Q, R2Q, R4Q, R6Q, R8Q,
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R10Q, R12Q, R14Q)> {
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let SubRegClasses = [(GR32 subreg_32bit, subreg_odd32),
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(GR64 subreg_even, subreg_odd)];
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}
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def FP32 : RegisterClass<"SystemZ", [f32], 32, (sequence "F%uS", 0, 15)>;
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def FP64 : RegisterClass<"SystemZ", [f64], 64, (sequence "F%uL", 0, 15)> {
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let SubRegClasses = [(FP32 subreg_32bit)];
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}
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// Status flags registers.
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def CCR : RegisterClass<"SystemZ", [i64], 64, (add PSW)> {
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let CopyCost = -1; // Don't allow copying of status registers.
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}
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