Jiangning Liu d7689b6ff6 [ARM64] Fix a bug in shuffle vector lowering to generate corect vext ISD with swapped input vectors. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209495 91177308-0d34-0410-b5e6-96231b3b80d8		2014-05-23 02:54:50 +00:00
..
AArch64	AArch64/ARM64: enable more AArch64 tests.	2014-05-22 07:40:55 +00:00
ARM	Segmented stacks: omit __morestack call when there's no frame.	2014-05-22 13:03:43 +00:00
ARM64	[ARM64] Fix a bug in shuffle vector lowering to generate corect vext ISD with swapped input vectors.	2014-05-23 02:54:50 +00:00
CPP
Generic	MC: move test from Generic to COFF	2014-04-23 21:41:07 +00:00
Hexagon	reverting r209132	2014-05-19 16:22:11 +00:00
Inputs
Mips	[mips] Make unalignedload.ll test stricter and easier to modify for MIPS32r6/MIPS64r6	2014-05-22 11:55:04 +00:00
MSP430	Mark FPB as a reserved register when needed.	2014-04-02 13:13:56 +00:00
NVPTX	Fix the test: DCE optimized away everything.	2014-04-21 17:23:12 +00:00
PowerPC	[PowerPC] PR19796: Also match ISD::TargetConstant in isIntS16Immediate	2014-05-20 17:20:34 +00:00
R600	R600: Try to convert BFE back to standard bit ops when possible.	2014-05-22 18:09:12 +00:00
SPARC	TableGen: fix operand counting for aliases	2014-05-16 09:42:04 +00:00
SystemZ	Reenable use of TBAA during CodeGen	2014-04-12 01:26:00 +00:00
Thumb	Segmented stacks: omit __morestack call when there's no frame.	2014-05-22 13:03:43 +00:00
Thumb2	Fix the Load/Store optimization pass to work with Thumb1.	2014-05-16 14:14:30 +00:00
X86	[X86] Improve the lowering of BITCAST from MVT::f64 to MVT::v4i16/MVT::v8i8.	2014-05-22 16:21:39 +00:00
XCore	Reapply "blockfreq: Rewrite BlockFrequencyInfoImpl"	2014-04-21 17:57:07 +00:00