llvm-6502/lib/CodeGen
2009-08-13 16:20:04 +00:00
..
AsmPrinter Various AsmWriter output cleanups. Use WriteAsOperand instead of 2009-08-13 01:36:44 +00:00
PBQP Remove unnecessary throw() specifications; LLVM doesn't use exceptions. 2009-08-11 15:35:57 +00:00
SelectionDAG Add callback to allow target to adjust latency of schedule dependency edge. 2009-08-13 16:05:04 +00:00
BranchFolding.cpp Rewrite previous patch to follow Chris' stylistic 2009-08-07 17:41:29 +00:00
CMakeLists.txt Post RA scheduler changes. Introduce a hazard recognizer that uses the target schedule information to accurately model the pipeline. Update the scheduler to correctly handle multi-issue targets. 2009-08-10 15:55:25 +00:00
CodePlacementOpt.cpp
DeadMachineInstructionElim.cpp Add const qualifiers. 2009-08-11 15:13:43 +00:00
Dump.cpp Re-apply LiveInterval index dumping patch, with fixes suggested by Bill 2009-08-03 21:55:09 +00:00
DwarfEHPrepare.cpp Move types back to the 2.5 API. 2009-07-29 22:17:13 +00:00
ELF.h ELF improvements: 2009-08-08 17:29:04 +00:00
ELFCodeEmitter.cpp - Remove custom handling of jumptables by the elf writter (this was 2009-08-05 06:57:03 +00:00
ELFCodeEmitter.h Change ELFCodeEmitter logic to emit the constant pool and jump tables to 2009-07-21 23:13:26 +00:00
ELFWriter.cpp Change MCSectionELF to represent a section semantically instead of 2009-08-13 05:07:35 +00:00
ELFWriter.h Move ConstantExpr handling to ResolveConstantExpr method and also 2009-08-10 03:32:40 +00:00
ExactHazardRecognizer.cpp Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one. 2009-08-12 18:31:53 +00:00
ExactHazardRecognizer.h Post RA scheduler changes. Introduce a hazard recognizer that uses the target schedule information to accurately model the pipeline. Update the scheduler to correctly handle multi-issue targets. 2009-08-10 15:55:25 +00:00
GCMetadata.cpp Remove Value::getName{Start,End}, the last of the old Name APIs. 2009-07-26 09:48:23 +00:00
GCMetadataPrinter.cpp
GCStrategy.cpp llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable. 2009-07-14 16:55:14 +00:00
IfConversion.cpp More migration to raw_ostream, the water has dried up around the iostream hole. 2009-07-25 00:23:56 +00:00
IntrinsicLowering.cpp Move a few more APIs back to 2.5 forms. The only remaining ones left to change back are 2009-07-31 20:28:14 +00:00
LatencyPriorityQueue.cpp
LazyLiveness.cpp Owen Anderson 2009-06-15: Use a SmallPtrSet here, for speed and to match df_iterator. 2009-06-15 22:54:48 +00:00
LiveInterval.cpp Modified VNInfo. The "copy" member is now a union which holds the copy for a register interval, or the defining register for a stack interval. Access is via getCopy/setCopy and getReg/setReg. 2009-08-10 23:43:28 +00:00
LiveIntervalAnalysis.cpp Modified VNInfo. The "copy" member is now a union which holds the copy for a register interval, or the defining register for a stack interval. Access is via getCopy/setCopy and getReg/setReg. 2009-08-10 23:43:28 +00:00
LiveStackAnalysis.cpp Update to in-place spilling framework. Includes live interval scaling and trivial rewriter. 2009-06-02 16:53:25 +00:00
LiveVariables.cpp Reapply r77654 with a fix: MachineFunctionPass's getAnalysisUsage 2009-07-31 18:16:33 +00:00
LLVMTargetMachine.cpp Change TargetAsmInfo to be constructed via TargetRegistry from a Target+Triple 2009-08-12 07:22:17 +00:00
LowerSubregs.cpp Remove RegisterScavenger::isSuperRegUsed(). This completely reverses the mistaken commit r77904. 2009-08-08 13:19:10 +00:00
MachineBasicBlock.cpp Re-apply LiveInterval index dumping patch, with fixes suggested by Bill 2009-08-03 21:55:09 +00:00
MachineDominators.cpp
MachineFunction.cpp Add MachineFrameInfo::getPristineRegisters(MBB) method. 2009-08-13 16:19:33 +00:00
MachineFunctionAnalysis.cpp Give MachineFunctionAnalysis a destructor so it can verify that 2009-08-01 04:19:43 +00:00
MachineFunctionPass.cpp Reapply r77654 with a fix: MachineFunctionPass's getAnalysisUsage 2009-07-31 18:16:33 +00:00
MachineInstr.cpp Don't tamper with <undef> operands in MachineInstr::addRegisterKilled. 2009-08-04 20:09:25 +00:00
MachineLICM.cpp Tidy #includes. 2009-08-11 16:02:12 +00:00
MachineLoopInfo.cpp Reapply r77654 with a fix: MachineFunctionPass's getAnalysisUsage 2009-07-31 18:16:33 +00:00
MachineModuleInfo.cpp Use setPreservesAll and setPreservesCFG in CodeGen passes. 2009-07-31 23:37:33 +00:00
MachinePassRegistry.cpp
MachineRegisterInfo.cpp Part 1. 2009-06-15 08:28:29 +00:00
MachineSink.cpp Various comment fixes. 2009-08-05 01:19:01 +00:00
MachineVerifier.cpp Use pristine register info in machine code verifier. 2009-08-13 16:19:51 +00:00
MachO.h Cleanup MachO writer and code emitter. Fix 80 cols problems, remove extra spaces, shrink down includes and move some methods out-of-line 2009-07-06 06:40:51 +00:00
MachOCodeEmitter.cpp Reapply my previous asmprinter changes now with more testing and two 2009-07-14 18:17:16 +00:00
MachOCodeEmitter.h Cleanup MachO writer and code emitter. Fix 80 cols problems, remove extra spaces, shrink down includes and move some methods out-of-line 2009-07-06 06:40:51 +00:00
MachOWriter.cpp Rename LessPrivateGlobalPrefix -> LinkerPrivateGlobalPrefix to match the 2009-07-21 17:30:51 +00:00
MachOWriter.h Match declaration to definition (missed a few). 2009-07-13 06:04:06 +00:00
Makefile
ObjectCodeEmitter.cpp Remove accidental commited comment 2009-08-05 07:00:43 +00:00
OcamlGC.cpp
Passes.cpp
PHIElimination.cpp Use setPreservesAll and setPreservesCFG in CodeGen passes. 2009-07-31 23:37:33 +00:00
PHIElimination.h Added PHI Def & Kill tracking to PHIElimination pass. 2009-07-23 04:34:03 +00:00
PostRASchedulerList.cpp Fix counting of Post-RA scheduling stalls. Improve debug output. 2009-08-12 21:47:46 +00:00
PreAllocSplitting.cpp Modified VNInfo. The "copy" member is now a union which holds the copy for a register interval, or the defining register for a stack interval. Access is via getCopy/setCopy and getReg/setReg. 2009-08-10 23:43:28 +00:00
PrologEpilogInserter.cpp Add MachineFrameInfo::getPristineRegisters(MBB) method. 2009-08-13 16:19:33 +00:00
PrologEpilogInserter.h Scan for presence of calls and determine max callframe size early. To allow ProcessFunctionBeforeCalleeSaveScan() use this information 2009-07-16 13:50:40 +00:00
PseudoSourceValue.cpp llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable. 2009-07-14 16:55:14 +00:00
README.txt
RegAllocLinearScan.cpp Use setPreservesAll and setPreservesCFG in CodeGen passes. 2009-07-31 23:37:33 +00:00
RegAllocLocal.cpp Use setPreservesAll and setPreservesCFG in CodeGen passes. 2009-07-31 23:37:33 +00:00
RegAllocPBQP.cpp Added RegisterCoalescer to required passes for PBQP. 2009-08-12 21:04:53 +00:00
RegAllocSimple.cpp Use setPreservesAll and setPreservesCFG in CodeGen passes. 2009-07-31 23:37:33 +00:00
RegisterCoalescer.cpp
RegisterScavenging.cpp Track pristine registers as if they were live-in in the register scavenger. 2009-08-13 16:20:04 +00:00
ScheduleDAG.cpp Add some debug output. 2009-08-11 17:35:23 +00:00
ScheduleDAGEmit.cpp
ScheduleDAGInstrs.cpp Add callback to allow target to adjust latency of schedule dependency edge. 2009-08-13 16:05:04 +00:00
ScheduleDAGInstrs.h
ScheduleDAGPrinter.cpp Switch to getNameStr(). 2009-07-24 08:24:36 +00:00
ShadowStackGC.cpp Privatize the StructType table, which unfortunately involves routing contexts through a number of APIs. 2009-08-05 23:16:16 +00:00
ShrinkWrapping.cpp More migration to raw_ostream, the water has dried up around the iostream hole. 2009-07-25 00:23:56 +00:00
SimpleHazardRecognizer.h Post RA scheduler changes. Introduce a hazard recognizer that uses the target schedule information to accurately model the pipeline. Update the scheduler to correctly handle multi-issue targets. 2009-08-10 15:55:25 +00:00
SimpleRegisterCoalescing.cpp Modified VNInfo. The "copy" member is now a union which holds the copy for a register interval, or the defining register for a stack interval. Access is via getCopy/setCopy and getReg/setReg. 2009-08-10 23:43:28 +00:00
SimpleRegisterCoalescing.h Simplify some more. 2009-07-17 21:06:58 +00:00
Spiller.cpp Improved tracking of value number kills. VN kills are now represented 2009-07-09 03:57:02 +00:00
Spiller.h Fix some minor MSVC compiler warnings. 2009-07-19 01:38:38 +00:00
StackProtector.cpp Revert yesterday's change by removing the LLVMContext parameter to AllocaInst and MallocInst. 2009-07-15 23:53:25 +00:00
StackSlotColoring.cpp Use setPreservesAll and setPreservesCFG in CodeGen passes. 2009-07-31 23:37:33 +00:00
StrongPHIElimination.cpp Modified VNInfo. The "copy" member is now a union which holds the copy for a register interval, or the defining register for a stack interval. Access is via getCopy/setCopy and getReg/setReg. 2009-08-10 23:43:28 +00:00
TargetInstrInfoImpl.cpp Let each target determines whether a machine instruction is dead. If true, that allows late codeine passes to delete it. 2009-07-22 00:25:27 +00:00
TwoAddressInstructionPass.cpp Code clean up. 2009-08-07 00:28:58 +00:00
UnreachableBlockElim.cpp Make UnreachableMachineBlockElim preserve MachineDominatorTree and 2009-08-01 00:34:30 +00:00
VirtRegMap.cpp Move more to raw_ostream, provide support for writing MachineBasicBlock, 2009-07-24 10:36:58 +00:00
VirtRegMap.h Move more to raw_ostream, provide support for writing MachineBasicBlock, 2009-07-24 10:36:58 +00:00
VirtRegRewriter.cpp Fix a bunch of namespace pollution. 2009-08-07 01:32:21 +00:00
VirtRegRewriter.h Fixed a bug in LiveInterval scaling (failure to scale VNI defs correctly), removed old TODO comments. 2009-06-24 02:17:32 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

I think we should have a "hasSideEffects" flag (which is automatically set for
stuff that "isLoad" "isCall" etc), and the remat pass should eventually be able
to remat any instruction that has no side effects, if it can handle it and if
profitable.

For now, I'd suggest having the remat stuff work like this:

1. I need to spill/reload this thing.
2. Check to see if it has side effects.
3. Check to see if it is simple enough: e.g. it only has one register
destination and no register input.
4. If so, clone the instruction, do the xform, etc.

Advantages of this are:

1. the .td file describes the behavior of the instructions, not the way the
   algorithm should work.
2. as remat gets smarter in the future, we shouldn't have to be changing the .td
   files.
3. it is easier to explain what the flag means in the .td file, because you
   don't have to pull in the explanation of how the current remat algo works.

Some potential added complexities:

1. Some instructions have to be glued to it's predecessor or successor. All of
   the PC relative instructions and condition code setting instruction. We could
   mark them as hasSideEffects, but that's not quite right. PC relative loads
   from constantpools can be remat'ed, for example. But it requires more than
   just cloning the instruction. Some instructions can be remat'ed but it
   expands to more than one instruction. But allocator will have to make a
   decision.

4. As stated in 3, not as simple as cloning in some cases. The target will have
   to decide how to remat it. For example, an ARM 2-piece constant generation
   instruction is remat'ed as a load from constantpool.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvments:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4