mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-28 04:29:44 +00:00
940f83e772
was inserted or not. This allows bitcast in fast isel to properly handle the case where an appropriate reg-to-reg copy is not available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55375 91177308-0d34-0410-b5e6-96231b3b80d8
439 lines
14 KiB
C++
439 lines
14 KiB
C++
//===- SPUInstrInfo.cpp - Cell SPU Instruction Information ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Cell SPU implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "SPURegisterNames.h"
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#include "SPUInstrInfo.h"
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#include "SPUInstrBuilder.h"
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#include "SPUTargetMachine.h"
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#include "SPUGenInstrInfo.inc"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Support/Streams.h"
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using namespace llvm;
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SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
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: TargetInstrInfoImpl(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0])),
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TM(tm),
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RI(*TM.getSubtargetImpl(), *this)
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{
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/* NOP */
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}
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/// getPointerRegClass - Return the register class to use to hold pointers.
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/// This is used for addressing modes.
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const TargetRegisterClass *
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SPUInstrInfo::getPointerRegClass() const
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{
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return &SPU::R32CRegClass;
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}
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bool
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SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
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unsigned& sourceReg,
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unsigned& destReg) const {
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// Primarily, ORI and OR are generated by copyRegToReg. But, there are other
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// cases where we can safely say that what's being done is really a move
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// (see how PowerPC does this -- it's the model for this code too.)
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switch (MI.getOpcode()) {
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default:
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break;
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case SPU::ORIv4i32:
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case SPU::ORIr32:
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case SPU::ORHIv8i16:
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case SPU::ORHIr16:
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case SPU::ORHIi8i16:
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case SPU::ORBIv16i8:
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case SPU::ORBIr8:
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case SPU::ORIi16i32:
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case SPU::ORIi8i32:
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case SPU::AHIvec:
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case SPU::AHIr16:
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case SPU::AIvec:
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assert(MI.getNumOperands() == 3 &&
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MI.getOperand(0).isRegister() &&
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MI.getOperand(1).isRegister() &&
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MI.getOperand(2).isImmediate() &&
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"invalid SPU ORI/ORHI/ORBI/AHI/AI/SFI/SFHI instruction!");
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if (MI.getOperand(2).getImm() == 0) {
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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break;
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case SPU::AIr32:
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assert(MI.getNumOperands() == 3 &&
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"wrong number of operands to AIr32");
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if (MI.getOperand(0).isRegister() &&
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(MI.getOperand(1).isRegister() ||
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MI.getOperand(1).isFrameIndex()) &&
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(MI.getOperand(2).isImmediate() &&
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MI.getOperand(2).getImm() == 0)) {
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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break;
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case SPU::ORv16i8_i8:
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case SPU::ORv8i16_i16:
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case SPU::ORv4i32_i32:
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case SPU::ORv2i64_i64:
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case SPU::ORv4f32_f32:
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case SPU::ORv2f64_f64:
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case SPU::ORi8_v16i8:
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case SPU::ORi16_v8i16:
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case SPU::ORi32_v4i32:
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case SPU::ORi64_v2i64:
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case SPU::ORf32_v4f32:
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case SPU::ORf64_v2f64:
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case SPU::ORv16i8:
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case SPU::ORv8i16:
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case SPU::ORv4i32:
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case SPU::ORr32:
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case SPU::ORr64:
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case SPU::ORf32:
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case SPU::ORf64:
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assert(MI.getNumOperands() == 3 &&
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MI.getOperand(0).isRegister() &&
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MI.getOperand(1).isRegister() &&
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MI.getOperand(2).isRegister() &&
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"invalid SPU OR(vec|r32|r64|gprc) instruction!");
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if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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break;
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}
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return false;
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}
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unsigned
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SPUInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const {
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switch (MI->getOpcode()) {
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default: break;
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case SPU::LQDv16i8:
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case SPU::LQDv8i16:
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case SPU::LQDv4i32:
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case SPU::LQDv4f32:
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case SPU::LQDv2f64:
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case SPU::LQDr128:
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case SPU::LQDr64:
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case SPU::LQDr32:
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case SPU::LQDr16:
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case SPU::LQXv4i32:
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case SPU::LQXr128:
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case SPU::LQXr64:
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case SPU::LQXr32:
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case SPU::LQXr16:
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if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
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MI->getOperand(2).isFrameIndex()) {
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FrameIndex = MI->getOperand(2).getIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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}
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return 0;
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}
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unsigned
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SPUInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
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switch (MI->getOpcode()) {
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default: break;
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case SPU::STQDv16i8:
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case SPU::STQDv8i16:
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case SPU::STQDv4i32:
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case SPU::STQDv4f32:
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case SPU::STQDv2f64:
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case SPU::STQDr128:
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case SPU::STQDr64:
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case SPU::STQDr32:
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case SPU::STQDr16:
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// case SPU::STQDr8:
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case SPU::STQXv16i8:
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case SPU::STQXv8i16:
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case SPU::STQXv4i32:
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case SPU::STQXv4f32:
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case SPU::STQXv2f64:
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case SPU::STQXr128:
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case SPU::STQXr64:
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case SPU::STQXr32:
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case SPU::STQXr16:
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// case SPU::STQXr8:
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if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
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MI->getOperand(2).isFrameIndex()) {
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FrameIndex = MI->getOperand(2).getIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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}
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return 0;
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}
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bool SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const
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{
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// We support cross register class moves for our aliases, such as R3 in any
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// reg class to any other reg class containing R3. This is required because
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// we instruction select bitconvert i64 -> f64 as a noop for example, so our
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// types have no specific meaning.
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//if (DestRC != SrcRC) {
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// cerr << "SPUInstrInfo::copyRegToReg(): DestRC != SrcRC not supported!\n";
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// abort();
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//}
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if (DestRC == SPU::R8CRegisterClass) {
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BuildMI(MBB, MI, get(SPU::ORBIr8), DestReg).addReg(SrcReg).addImm(0);
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} else if (DestRC == SPU::R16CRegisterClass) {
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BuildMI(MBB, MI, get(SPU::ORHIr16), DestReg).addReg(SrcReg).addImm(0);
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} else if (DestRC == SPU::R32CRegisterClass) {
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BuildMI(MBB, MI, get(SPU::ORIr32), DestReg).addReg(SrcReg).addImm(0);
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} else if (DestRC == SPU::R32FPRegisterClass) {
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BuildMI(MBB, MI, get(SPU::ORf32), DestReg).addReg(SrcReg)
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.addReg(SrcReg);
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} else if (DestRC == SPU::R64CRegisterClass) {
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BuildMI(MBB, MI, get(SPU::ORr64), DestReg).addReg(SrcReg)
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.addReg(SrcReg);
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} else if (DestRC == SPU::R64FPRegisterClass) {
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BuildMI(MBB, MI, get(SPU::ORf64), DestReg).addReg(SrcReg)
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.addReg(SrcReg);
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} /* else if (DestRC == SPU::GPRCRegisterClass) {
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BuildMI(MBB, MI, get(SPU::ORgprc), DestReg).addReg(SrcReg)
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.addReg(SrcReg);
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} */ else if (DestRC == SPU::VECREGRegisterClass) {
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BuildMI(MBB, MI, get(SPU::ORv4i32), DestReg).addReg(SrcReg)
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.addReg(SrcReg);
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} else {
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// Attempt to copy unknown/unsupported register class!
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return false;
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}
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return true;
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}
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void
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SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill, int FrameIdx,
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const TargetRegisterClass *RC) const
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{
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unsigned opc;
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if (RC == SPU::GPRCRegisterClass) {
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opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
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? SPU::STQDr128
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: SPU::STQXr128;
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} else if (RC == SPU::R64CRegisterClass) {
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opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
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? SPU::STQDr64
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: SPU::STQXr64;
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} else if (RC == SPU::R64FPRegisterClass) {
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opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
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? SPU::STQDr64
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: SPU::STQXr64;
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} else if (RC == SPU::R32CRegisterClass) {
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opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
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? SPU::STQDr32
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: SPU::STQXr32;
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} else if (RC == SPU::R32FPRegisterClass) {
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opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
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? SPU::STQDr32
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: SPU::STQXr32;
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} else if (RC == SPU::R16CRegisterClass) {
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opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) ?
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SPU::STQDr16
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: SPU::STQXr16;
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} else {
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assert(0 && "Unknown regclass!");
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abort();
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}
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addFrameReference(BuildMI(MBB, MI, get(opc))
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.addReg(SrcReg, false, false, isKill), FrameIdx);
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}
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void SPUInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
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bool isKill,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const {
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cerr << "storeRegToAddr() invoked!\n";
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abort();
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if (Addr[0].isFrameIndex()) {
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/* do what storeRegToStackSlot does here */
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} else {
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unsigned Opc = 0;
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if (RC == SPU::GPRCRegisterClass) {
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/* Opc = PPC::STW; */
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} else if (RC == SPU::R16CRegisterClass) {
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/* Opc = PPC::STD; */
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} else if (RC == SPU::R32CRegisterClass) {
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/* Opc = PPC::STFD; */
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} else if (RC == SPU::R32FPRegisterClass) {
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/* Opc = PPC::STFD; */
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} else if (RC == SPU::R64FPRegisterClass) {
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/* Opc = PPC::STFS; */
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} else if (RC == SPU::VECREGRegisterClass) {
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/* Opc = PPC::STVX; */
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} else {
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assert(0 && "Unknown regclass!");
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abort();
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}
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MachineInstrBuilder MIB = BuildMI(MF, get(Opc))
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.addReg(SrcReg, false, false, isKill);
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for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
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MachineOperand &MO = Addr[i];
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if (MO.isRegister())
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MIB.addReg(MO.getReg());
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else if (MO.isImmediate())
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MIB.addImm(MO.getImm());
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else
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MIB.addFrameIndex(MO.getIndex());
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}
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NewMIs.push_back(MIB);
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}
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}
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void
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SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC) const
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{
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unsigned opc;
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if (RC == SPU::GPRCRegisterClass) {
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opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
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? SPU::LQDr128
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: SPU::LQXr128;
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} else if (RC == SPU::R64CRegisterClass) {
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opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
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? SPU::LQDr64
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: SPU::LQXr64;
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} else if (RC == SPU::R64FPRegisterClass) {
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opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
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? SPU::LQDr64
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: SPU::LQXr64;
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} else if (RC == SPU::R32CRegisterClass) {
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opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
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? SPU::LQDr32
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: SPU::LQXr32;
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} else if (RC == SPU::R32FPRegisterClass) {
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opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
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? SPU::LQDr32
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: SPU::LQXr32;
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} else if (RC == SPU::R16CRegisterClass) {
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opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
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? SPU::LQDr16
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: SPU::LQXr16;
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} else {
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assert(0 && "Unknown regclass in loadRegFromStackSlot!");
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abort();
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}
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addFrameReference(BuildMI(MBB, MI, get(opc)).addReg(DestReg), FrameIdx);
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}
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/*!
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\note We are really pessimistic here about what kind of a load we're doing.
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*/
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void SPUInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs)
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const {
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cerr << "loadRegToAddr() invoked!\n";
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abort();
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if (Addr[0].isFrameIndex()) {
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/* do what loadRegFromStackSlot does here... */
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} else {
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unsigned Opc = 0;
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if (RC == SPU::R8CRegisterClass) {
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/* do brilliance here */
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} else if (RC == SPU::R16CRegisterClass) {
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/* Opc = PPC::LWZ; */
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} else if (RC == SPU::R32CRegisterClass) {
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/* Opc = PPC::LD; */
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} else if (RC == SPU::R32FPRegisterClass) {
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/* Opc = PPC::LFD; */
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} else if (RC == SPU::R64FPRegisterClass) {
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/* Opc = PPC::LFS; */
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} else if (RC == SPU::VECREGRegisterClass) {
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/* Opc = PPC::LVX; */
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} else if (RC == SPU::GPRCRegisterClass) {
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/* Opc = something else! */
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} else {
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assert(0 && "Unknown regclass!");
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abort();
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}
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MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
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for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
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MachineOperand &MO = Addr[i];
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if (MO.isRegister())
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MIB.addReg(MO.getReg());
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else if (MO.isImmediate())
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MIB.addImm(MO.getImm());
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else
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MIB.addFrameIndex(MO.getIndex());
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}
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NewMIs.push_back(MIB);
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}
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}
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/// foldMemoryOperand - SPU, like PPC, can only fold spills into
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/// copy instructions, turning them into load/store instructions.
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MachineInstr *
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SPUInstrInfo::foldMemoryOperand(MachineFunction &MF,
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MachineInstr *MI,
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SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const
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{
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#if SOMEDAY_SCOTT_LOOKS_AT_ME_AGAIN
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if (Ops.size() != 1) return NULL;
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unsigned OpNum = Ops[0];
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unsigned Opc = MI->getOpcode();
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MachineInstr *NewMI = 0;
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if ((Opc == SPU::ORr32
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|| Opc == SPU::ORv4i32)
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&& MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
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if (OpNum == 0) { // move -> store
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unsigned InReg = MI->getOperand(1).getReg();
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bool isKill = MI->getOperand(1).isKill();
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if (FrameIndex < SPUFrameInfo::maxFrameOffset()) {
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NewMI = addFrameReference(BuildMI(MF, TII.get(SPU::STQDr32))
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.addReg(InReg, false, false, isKill),
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FrameIndex);
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}
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} else { // move -> load
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unsigned OutReg = MI->getOperand(0).getReg();
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bool isDead = MI->getOperand(0).isDead();
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Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset())
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? SPU::STQDr32 : SPU::STQXr32;
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NewMI = addFrameReference(BuildMI(MF, TII.get(Opc))
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.addReg(OutReg, true, false, false, isDead), FrameIndex);
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}
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}
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return NewMI;
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#else
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return 0;
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#endif
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}
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