Elena Demikhovsky f4623cee34 AVX-512: fixed comressed displacement - by Robert Khazanov ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203096 91177308-0d34-0410-b5e6-96231b3b80d8

2014-03-06 08:15:35 +00:00

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AlignedBundling

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3DNow.s

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2011-09-06-NoNewline.s

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address-size.s

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avx512-encodings.s

AVX-512: fixed comressed displacement - by Robert Khazanov

2014-03-06 08:15:35 +00:00

cfi_def_cfa-crash.s

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fde-reloc.s

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fixup-cpu-mode.s

Tests for mode switching

2014-01-28 23:13:30 +00:00

gnux32-dwarf-gen.s

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index-operations.s

[x86] Allow segment and address-size overrides for INS[BWLQ] (PR9385)

2014-01-22 15:08:55 +00:00

intel-syntax-2.s

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intel-syntax-avx512.s

Teach X86 asm parser to understand 'ZMMWORD PTR' in Intel syntax.

2014-01-17 07:37:39 +00:00

intel-syntax-bitwise-ops.s

Update the X86 assembler for .intel_syntax to accept

2014-02-06 01:21:15 +00:00

intel-syntax-directional-label.s

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intel-syntax-encoding.s

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intel-syntax-hex.s

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intel-syntax-invalid-basereg.s

Update the X86 assembler for .intel_syntax to produce an error for invalid base

2014-01-23 22:34:42 +00:00

intel-syntax-invalid-scale.s

Update the X86 assembler for .intel_syntax to produce an error for invalid

2014-01-23 21:52:41 +00:00

intel-syntax.s

MC: Fix Intel assembly parser for [global + offset]

2014-03-04 00:33:17 +00:00

lit.local.cfg

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padlock.s

Remove special FP opcode maps and instead add enough MRM_XX formats to handle all the FP operations. This increases format by 1 bit, but decreases opcode map by 1 bit so the TSFlags size doesn't change.

2014-02-19 08:25:02 +00:00

relax-insn.s

[x86] Do not relax PUSHi16 to PUSHi32 (PR18414)

2014-01-08 12:58:32 +00:00

ret.s

[x86] Support i386-*-*-code16 triple for emitting 16-bit code

2014-01-20 12:02:25 +00:00

shuffle-comments.s

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stackmap-nops.ll

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variant-diagnostics.s

MC: fix test locations/name

2014-01-26 22:55:02 +00:00

x86_64-avx-clmul-encoding.s

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x86_64-avx-encoding.s

Move address override handling in X86MCCodeEmitter to a place where it works for VEX encoded instructions too. This allows 32-bit addressing to work in 64-bit mode.

2014-01-31 05:33:45 +00:00

x86_64-bmi-encoding.s

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x86_64-encoding.s

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x86_64-fma3-encoding.s

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x86_64-fma4-encoding.s

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x86_64-hle-encoding.s

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x86_64-imm-widths.s

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x86_64-rand-encoding.s

Add support of RDSEED defined in AVX2 extension

2013-03-28 23:41:26 +00:00

x86_64-rtm-encoding.s

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x86_64-signed-reloc.s

[x86] Fix signed relocations for i64i32imm operands

2014-01-30 22:20:41 +00:00

x86_64-sse4a.s

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x86_64-tbm-encoding.s

Move address override handling in X86MCCodeEmitter to a place where it works for VEX encoded instructions too. This allows 32-bit addressing to work in 64-bit mode.

2014-01-31 05:33:45 +00:00

x86_64-xop-encoding.s

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x86_directives.s

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x86_errors.s

[x86] Make AsmParser validate registers for memory operands a bit better

2014-01-08 12:58:28 +00:00

x86_long_nop.s

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x86_nop.s

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x86_operands.s

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x86-16.s

[x86] Allow segment and address-size overrides for INS[BWLQ] (PR9385)

2014-01-22 15:08:55 +00:00

x86-32-avx.s

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x86-32-coverage.s

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x86-32-fma3.s

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x86-32-ms-inline-asm.s

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x86-32.s

[x86] Allow segment and address-size overrides for INS[BWLQ] (PR9385)

2014-01-22 15:08:55 +00:00

x86-64.s

Recommit r201059 and r201060 with hopefully a fix for its original failure.

2014-02-10 06:55:41 +00:00

x86-target-directives.s

correct target directive handling error handling

2014-01-13 01:15:39 +00:00