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286fbd19f3
have target lowering take the subtarget explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213426 91177308-0d34-0410-b5e6-96231b3b80d8
82 lines
2.9 KiB
C++
82 lines
2.9 KiB
C++
//===-- Mips16ISelLowering.h - Mips16 DAG Lowering Interface ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Subclass of MipsTargetLowering specialized for mips16.
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//
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//===----------------------------------------------------------------------===//
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#ifndef MIPS16ISELLOWERING_H
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#define MIPS16ISELLOWERING_H
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#include "MipsISelLowering.h"
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namespace llvm {
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class Mips16TargetLowering : public MipsTargetLowering {
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public:
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explicit Mips16TargetLowering(MipsTargetMachine &TM,
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const MipsSubtarget &STI);
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bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
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bool *Fast) const override;
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MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB) const override;
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private:
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bool isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
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unsigned NextStackOffset,
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const MipsFunctionInfo& FI) const override;
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void setMips16HardFloatLibCalls();
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unsigned int
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getMips16HelperFunctionStubNumber(ArgListTy &Args) const;
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const char *getMips16HelperFunction
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(Type* RetTy, ArgListTy &Args, bool &needHelper) const;
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void
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getOpndList(SmallVectorImpl<SDValue> &Ops,
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std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
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bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
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CallLoweringInfo &CLI, SDValue Callee,
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SDValue Chain) const override;
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MachineBasicBlock *emitSel16(unsigned Opc, MachineInstr *MI,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *emitSeliT16(unsigned Opc1, unsigned Opc2,
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MachineInstr *MI,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *emitSelT16(unsigned Opc1, unsigned Opc2,
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MachineInstr *MI,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc,
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MachineInstr *MI,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *emitFEXT_T8I8I16_ins(
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unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc, bool ImmSigned,
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MachineInstr *MI, MachineBasicBlock *BB) const;
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MachineBasicBlock *emitFEXT_CCRX16_ins(
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unsigned SltOpc,
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MachineInstr *MI, MachineBasicBlock *BB) const;
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MachineBasicBlock *emitFEXT_CCRXI16_ins(
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unsigned SltiOpc, unsigned SltiXOpc,
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MachineInstr *MI, MachineBasicBlock *BB )const;
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};
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}
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#endif // Mips16ISELLOWERING_H
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