Jim Grosbach 580f4a9c1c ARM assembly parsing and encoding for SSAT instruction. ... Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the shift operand to correctly handle the allowed shift types and immediate ranges and issue meaningful diagnostics when an illegal value or shift type is specified. Add aliases to parse an ommitted shift operand (default value of 'lsl #0'). Add tests for diagnostics and proper encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135990 91177308-0d34-0410-b5e6-96231b3b80d8		2011-07-25 22:20:28 +00:00
..
ARMDisassembler.cpp	Fix typo in the comment.	2011-04-19 23:58:52 +00:00
ARMDisassembler.h	Better error handling of invalid IT mask '0000', instead of just asserting.	2010-04-19 23:02:58 +00:00
ARMDisassemblerCore.cpp	ARM assembly parsing and encoding for SSAT instruction.	2011-07-25 22:20:28 +00:00
ARMDisassemblerCore.h	Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits.	2011-07-21 23:38:37 +00:00
CMakeLists.txt	CMake: Add disabling optimization on MSVC8 and MSVC10 as workaround for some files in Target/ARM and Target/X86.	2010-12-29 03:59:27 +00:00
Makefile
ThumbDisassemblerCore.h	ARM assembly parsing and encoding for SSAT instruction.	2011-07-25 22:20:28 +00:00