llvm-6502/test/CodeGen
Elena Demikhovsky 05e61f7113 X86: optimized i64 vector multiply with constant
When we multiply two 64-bit vectors, we extract lower and upper part and use the PMULUDQ instruction.
When one of the operands is a constant, the upper part may be zero, we know this at compile time.
Example: %a = mul <4 x i64> %b, <4 x i64> < i64 5, i64 5, i64 5, i64 5>.
I'm checking the value of the upper part and prevent redundant "multiply", "shift" and "add" operations.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239802 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-16 06:07:24 +00:00
..
AArch64 [AArch64] Generalize extract-high DUP extension to MOVI/MVNI. 2015-06-16 01:18:14 +00:00
AMDGPU
ARM
BPF
CPP
Generic
Hexagon [Hexagon] Using readobj rather than objdump. 2015-06-15 21:57:41 +00:00
Inputs
Mips
MIR MIR Serialization: Print and parse simple machine function attributes. 2015-06-16 00:10:47 +00:00
MSP430
NVPTX Revert 239795 2015-06-16 01:20:53 +00:00
PowerPC
SPARC
SystemZ
Thumb
Thumb2
WinEH
X86 X86: optimized i64 vector multiply with constant 2015-06-16 06:07:24 +00:00
XCore