mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-26 07:29:55 +00:00
Print in decimal for inline immediates, and hex otherwise. Use hex always for offsets in addressing offsets. This approximately matches what the shader compiler does. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206335 91177308-0d34-0410-b5e6-96231b3b80d8
456 lines
14 KiB
LLVM
456 lines
14 KiB
LLVM
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK
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; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG-CHECK
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; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
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; EG-CHECK-LABEL: @i8_arg
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; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
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; SI-CHECK-LABEL: @i8_arg
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; SI-CHECK: BUFFER_LOAD_UBYTE
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define void @i8_arg(i32 addrspace(1)* nocapture %out, i8 %in) nounwind {
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entry:
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%0 = zext i8 %in to i32
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store i32 %0, i32 addrspace(1)* %out, align 4
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ret void
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}
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; EG-CHECK-LABEL: @i8_zext_arg
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; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
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; SI-CHECK-LABEL: @i8_zext_arg
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; SI-CHECK: S_LOAD_DWORD s{{[0-9]}}, s[0:1], 0xb
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define void @i8_zext_arg(i32 addrspace(1)* nocapture %out, i8 zeroext %in) nounwind {
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entry:
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%0 = zext i8 %in to i32
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store i32 %0, i32 addrspace(1)* %out, align 4
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ret void
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}
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; EG-CHECK-LABEL: @i8_sext_arg
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; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
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; SI-CHECK-LABEL: @i8_sext_arg
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; SI-CHECK: S_LOAD_DWORD s{{[0-9]}}, s[0:1], 0xb
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define void @i8_sext_arg(i32 addrspace(1)* nocapture %out, i8 signext %in) nounwind {
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entry:
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%0 = sext i8 %in to i32
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store i32 %0, i32 addrspace(1)* %out, align 4
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ret void
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}
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; EG-CHECK-LABEL: @i16_arg
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; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
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; SI-CHECK-LABEL: @i16_arg
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; SI-CHECK: BUFFER_LOAD_USHORT
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define void @i16_arg(i32 addrspace(1)* nocapture %out, i16 %in) nounwind {
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entry:
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%0 = zext i16 %in to i32
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store i32 %0, i32 addrspace(1)* %out, align 4
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ret void
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}
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; EG-CHECK-LABEL: @i16_zext_arg
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; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
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; SI-CHECK-LABEL: @i16_zext_arg
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; SI-CHECK: S_LOAD_DWORD s{{[0-9]}}, s[0:1], 0xb
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define void @i16_zext_arg(i32 addrspace(1)* nocapture %out, i16 zeroext %in) nounwind {
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entry:
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%0 = zext i16 %in to i32
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store i32 %0, i32 addrspace(1)* %out, align 4
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ret void
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}
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; EG-CHECK-LABEL: @i16_sext_arg
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; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
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; SI-CHECK-LABEL: @i16_sext_arg
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; SI-CHECK: S_LOAD_DWORD s{{[0-9]}}, s[0:1], 0xb
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define void @i16_sext_arg(i32 addrspace(1)* nocapture %out, i16 signext %in) nounwind {
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entry:
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%0 = sext i16 %in to i32
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store i32 %0, i32 addrspace(1)* %out, align 4
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ret void
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}
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; EG-CHECK-LABEL: @i32_arg
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; EG-CHECK: T{{[0-9]\.[XYZW]}}, KC0[2].Z
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; SI-CHECK-LABEL: @i32_arg
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; S_LOAD_DWORD s{{[0-9]}}, s[0:1], 0xb
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define void @i32_arg(i32 addrspace(1)* nocapture %out, i32 %in) nounwind {
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entry:
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store i32 %in, i32 addrspace(1)* %out, align 4
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ret void
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}
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; EG-CHECK-LABEL: @f32_arg
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; EG-CHECK: T{{[0-9]\.[XYZW]}}, KC0[2].Z
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; SI-CHECK-LABEL: @f32_arg
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; S_LOAD_DWORD s{{[0-9]}}, s[0:1], 0xb
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define void @f32_arg(float addrspace(1)* nocapture %out, float %in) nounwind {
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entry:
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store float %in, float addrspace(1)* %out, align 4
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ret void
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}
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; EG-CHECK-LABEL: @v2i8_arg
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; EG-CHECK: VTX_READ_8
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; EG-CHECK: VTX_READ_8
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; SI-CHECK-LABEL: @v2i8_arg
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; SI-CHECK: BUFFER_LOAD_UBYTE
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; SI-CHECK: BUFFER_LOAD_UBYTE
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define void @v2i8_arg(<2 x i8> addrspace(1)* %out, <2 x i8> %in) {
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entry:
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store <2 x i8> %in, <2 x i8> addrspace(1)* %out
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ret void
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}
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; EG-CHECK-LABEL: @v2i16_arg
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; EG-CHECK: VTX_READ_16
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; EG-CHECK: VTX_READ_16
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; SI-CHECK-LABEL: @v2i16_arg
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; SI-CHECK-DAG: BUFFER_LOAD_USHORT
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; SI-CHECK-DAG: BUFFER_LOAD_USHORT
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define void @v2i16_arg(<2 x i16> addrspace(1)* %out, <2 x i16> %in) {
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entry:
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store <2 x i16> %in, <2 x i16> addrspace(1)* %out
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ret void
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}
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; EG-CHECK-LABEL: @v2i32_arg
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W
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; SI-CHECK-LABEL: @v2i32_arg
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; SI-CHECK: S_LOAD_DWORDX2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xb
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define void @v2i32_arg(<2 x i32> addrspace(1)* nocapture %out, <2 x i32> %in) nounwind {
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entry:
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store <2 x i32> %in, <2 x i32> addrspace(1)* %out, align 4
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ret void
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}
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; EG-CHECK-LABEL: @v2f32_arg
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W
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; SI-CHECK-LABEL: @v2f32_arg
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; SI-CHECK: S_LOAD_DWORDX2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xb
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define void @v2f32_arg(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) nounwind {
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entry:
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store <2 x float> %in, <2 x float> addrspace(1)* %out, align 4
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ret void
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}
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; EG-CHECK-LABEL: @v3i8_arg
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; VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 40
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; VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 41
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; VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 42
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; SI-CHECK-LABEL: @v3i8_arg
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define void @v3i8_arg(<3 x i8> addrspace(1)* nocapture %out, <3 x i8> %in) nounwind {
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entry:
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store <3 x i8> %in, <3 x i8> addrspace(1)* %out, align 4
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ret void
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}
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; EG-CHECK-LABEL: @v3i16_arg
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; VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 44
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; VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 46
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; VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 48
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; SI-CHECK-LABEL: @v3i16_arg
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define void @v3i16_arg(<3 x i16> addrspace(1)* nocapture %out, <3 x i16> %in) nounwind {
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entry:
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store <3 x i16> %in, <3 x i16> addrspace(1)* %out, align 4
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ret void
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}
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; EG-CHECK-LABEL: @v3i32_arg
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W
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; SI-CHECK-LABEL: @v3i32_arg
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; SI-CHECK: S_LOAD_DWORDX4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0xd
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define void @v3i32_arg(<3 x i32> addrspace(1)* nocapture %out, <3 x i32> %in) nounwind {
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entry:
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store <3 x i32> %in, <3 x i32> addrspace(1)* %out, align 4
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ret void
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}
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; EG-CHECK-LABEL: @v3f32_arg
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W
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; SI-CHECK-LABEL: @v3f32_arg
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; SI-CHECK: S_LOAD_DWORDX4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0xd
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define void @v3f32_arg(<3 x float> addrspace(1)* nocapture %out, <3 x float> %in) nounwind {
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entry:
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store <3 x float> %in, <3 x float> addrspace(1)* %out, align 4
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ret void
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}
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; EG-CHECK-LABEL: @v4i8_arg
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; EG-CHECK: VTX_READ_8
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; EG-CHECK: VTX_READ_8
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; EG-CHECK: VTX_READ_8
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; EG-CHECK: VTX_READ_8
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; SI-CHECK-LABEL: @v4i8_arg
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; SI-CHECK: BUFFER_LOAD_UBYTE
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; SI-CHECK: BUFFER_LOAD_UBYTE
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; SI-CHECK: BUFFER_LOAD_UBYTE
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; SI-CHECK: BUFFER_LOAD_UBYTE
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define void @v4i8_arg(<4 x i8> addrspace(1)* %out, <4 x i8> %in) {
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entry:
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store <4 x i8> %in, <4 x i8> addrspace(1)* %out
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ret void
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}
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; EG-CHECK-LABEL: @v4i16_arg
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; EG-CHECK: VTX_READ_16
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; EG-CHECK: VTX_READ_16
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; EG-CHECK: VTX_READ_16
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; EG-CHECK: VTX_READ_16
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; SI-CHECK-LABEL: @v4i16_arg
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; SI-CHECK: BUFFER_LOAD_USHORT
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; SI-CHECK: BUFFER_LOAD_USHORT
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; SI-CHECK: BUFFER_LOAD_USHORT
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; SI-CHECK: BUFFER_LOAD_USHORT
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define void @v4i16_arg(<4 x i16> addrspace(1)* %out, <4 x i16> %in) {
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entry:
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store <4 x i16> %in, <4 x i16> addrspace(1)* %out
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ret void
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}
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; EG-CHECK-LABEL: @v4i32_arg
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X
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; SI-CHECK-LABEL: @v4i32_arg
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; SI-CHECK: S_LOAD_DWORDX4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xd
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define void @v4i32_arg(<4 x i32> addrspace(1)* nocapture %out, <4 x i32> %in) nounwind {
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entry:
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store <4 x i32> %in, <4 x i32> addrspace(1)* %out, align 4
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ret void
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}
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; EG-CHECK-LABEL: @v4f32_arg
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X
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; SI-CHECK-LABEL: @v4f32_arg
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; SI-CHECK: S_LOAD_DWORDX4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xd
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define void @v4f32_arg(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) nounwind {
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entry:
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store <4 x float> %in, <4 x float> addrspace(1)* %out, align 4
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ret void
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}
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; EG-CHECK-LABEL: @v8i8_arg
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; EG-CHECK: VTX_READ_8
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; EG-CHECK: VTX_READ_8
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; EG-CHECK: VTX_READ_8
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; EG-CHECK: VTX_READ_8
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; EG-CHECK: VTX_READ_8
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; EG-CHECK: VTX_READ_8
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; EG-CHECK: VTX_READ_8
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; EG-CHECK: VTX_READ_8
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; SI-CHECK-LABEL: @v8i8_arg
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; SI-CHECK: BUFFER_LOAD_UBYTE
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; SI-CHECK: BUFFER_LOAD_UBYTE
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; SI-CHECK: BUFFER_LOAD_UBYTE
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; SI-CHECK: BUFFER_LOAD_UBYTE
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; SI-CHECK: BUFFER_LOAD_UBYTE
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; SI-CHECK: BUFFER_LOAD_UBYTE
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; SI-CHECK: BUFFER_LOAD_UBYTE
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define void @v8i8_arg(<8 x i8> addrspace(1)* %out, <8 x i8> %in) {
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entry:
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store <8 x i8> %in, <8 x i8> addrspace(1)* %out
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ret void
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}
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; EG-CHECK-LABEL: @v8i16_arg
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; EG-CHECK: VTX_READ_16
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; EG-CHECK: VTX_READ_16
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; EG-CHECK: VTX_READ_16
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; EG-CHECK: VTX_READ_16
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; EG-CHECK: VTX_READ_16
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; EG-CHECK: VTX_READ_16
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; EG-CHECK: VTX_READ_16
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; EG-CHECK: VTX_READ_16
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; SI-CHECK-LABEL: @v8i16_arg
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; SI-CHECK: BUFFER_LOAD_USHORT
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; SI-CHECK: BUFFER_LOAD_USHORT
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; SI-CHECK: BUFFER_LOAD_USHORT
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; SI-CHECK: BUFFER_LOAD_USHORT
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; SI-CHECK: BUFFER_LOAD_USHORT
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; SI-CHECK: BUFFER_LOAD_USHORT
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; SI-CHECK: BUFFER_LOAD_USHORT
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; SI-CHECK: BUFFER_LOAD_USHORT
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define void @v8i16_arg(<8 x i16> addrspace(1)* %out, <8 x i16> %in) {
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entry:
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store <8 x i16> %in, <8 x i16> addrspace(1)* %out
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ret void
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}
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; EG-CHECK-LABEL: @v8i32_arg
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Y
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Z
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].W
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].X
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Y
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Z
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].W
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].X
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; SI-CHECK-LABEL: @v8i32_arg
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; SI-CHECK: S_LOAD_DWORDX8 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x11
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define void @v8i32_arg(<8 x i32> addrspace(1)* nocapture %out, <8 x i32> %in) nounwind {
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entry:
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store <8 x i32> %in, <8 x i32> addrspace(1)* %out, align 4
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ret void
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}
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; EG-CHECK-LABEL: @v8f32_arg
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Y
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Z
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].W
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].X
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Y
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Z
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].W
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].X
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; SI-CHECK-LABEL: @v8f32_arg
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; SI-CHECK: S_LOAD_DWORDX8 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x11
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define void @v8f32_arg(<8 x float> addrspace(1)* nocapture %out, <8 x float> %in) nounwind {
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entry:
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store <8 x float> %in, <8 x float> addrspace(1)* %out, align 4
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ret void
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}
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; EG-CHECK-LABEL: @v16i8_arg
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; EG-CHECK: VTX_READ_8
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; EG-CHECK: VTX_READ_8
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; EG-CHECK: VTX_READ_8
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; EG-CHECK: VTX_READ_8
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; EG-CHECK: VTX_READ_8
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; EG-CHECK: VTX_READ_8
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; EG-CHECK: VTX_READ_8
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; EG-CHECK: VTX_READ_8
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; EG-CHECK: VTX_READ_8
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; EG-CHECK: VTX_READ_8
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; EG-CHECK: VTX_READ_8
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; EG-CHECK: VTX_READ_8
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; EG-CHECK: VTX_READ_8
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; EG-CHECK: VTX_READ_8
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; EG-CHECK: VTX_READ_8
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; EG-CHECK: VTX_READ_8
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; SI-CHECK-LABEL: @v16i8_arg
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; SI-CHECK: BUFFER_LOAD_UBYTE
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; SI-CHECK: BUFFER_LOAD_UBYTE
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; SI-CHECK: BUFFER_LOAD_UBYTE
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; SI-CHECK: BUFFER_LOAD_UBYTE
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; SI-CHECK: BUFFER_LOAD_UBYTE
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; SI-CHECK: BUFFER_LOAD_UBYTE
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; SI-CHECK: BUFFER_LOAD_UBYTE
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; SI-CHECK: BUFFER_LOAD_UBYTE
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; SI-CHECK: BUFFER_LOAD_UBYTE
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; SI-CHECK: BUFFER_LOAD_UBYTE
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; SI-CHECK: BUFFER_LOAD_UBYTE
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; SI-CHECK: BUFFER_LOAD_UBYTE
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; SI-CHECK: BUFFER_LOAD_UBYTE
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; SI-CHECK: BUFFER_LOAD_UBYTE
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; SI-CHECK: BUFFER_LOAD_UBYTE
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; SI-CHECK: BUFFER_LOAD_UBYTE
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define void @v16i8_arg(<16 x i8> addrspace(1)* %out, <16 x i8> %in) {
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entry:
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store <16 x i8> %in, <16 x i8> addrspace(1)* %out
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ret void
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}
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; EG-CHECK-LABEL: @v16i16_arg
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; EG-CHECK: VTX_READ_16
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; EG-CHECK: VTX_READ_16
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; EG-CHECK: VTX_READ_16
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; EG-CHECK: VTX_READ_16
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; EG-CHECK: VTX_READ_16
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; EG-CHECK: VTX_READ_16
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; EG-CHECK: VTX_READ_16
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; EG-CHECK: VTX_READ_16
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; EG-CHECK: VTX_READ_16
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; EG-CHECK: VTX_READ_16
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; EG-CHECK: VTX_READ_16
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; EG-CHECK: VTX_READ_16
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; EG-CHECK: VTX_READ_16
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; EG-CHECK: VTX_READ_16
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; EG-CHECK: VTX_READ_16
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; EG-CHECK: VTX_READ_16
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; SI-CHECK-LABEL: @v16i16_arg
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; SI-CHECK: BUFFER_LOAD_USHORT
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; SI-CHECK: BUFFER_LOAD_USHORT
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; SI-CHECK: BUFFER_LOAD_USHORT
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; SI-CHECK: BUFFER_LOAD_USHORT
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; SI-CHECK: BUFFER_LOAD_USHORT
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; SI-CHECK: BUFFER_LOAD_USHORT
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; SI-CHECK: BUFFER_LOAD_USHORT
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; SI-CHECK: BUFFER_LOAD_USHORT
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; SI-CHECK: BUFFER_LOAD_USHORT
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; SI-CHECK: BUFFER_LOAD_USHORT
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; SI-CHECK: BUFFER_LOAD_USHORT
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; SI-CHECK: BUFFER_LOAD_USHORT
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; SI-CHECK: BUFFER_LOAD_USHORT
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; SI-CHECK: BUFFER_LOAD_USHORT
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; SI-CHECK: BUFFER_LOAD_USHORT
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; SI-CHECK: BUFFER_LOAD_USHORT
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define void @v16i16_arg(<16 x i16> addrspace(1)* %out, <16 x i16> %in) {
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entry:
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store <16 x i16> %in, <16 x i16> addrspace(1)* %out
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ret void
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}
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; EG-CHECK-LABEL: @v16i32_arg
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Y
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Z
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].W
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].X
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Y
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Z
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].W
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].X
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Y
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Z
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].W
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].X
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Y
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Z
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].W
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X
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; SI-CHECK-LABEL: @v16i32_arg
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; SI-CHECK: S_LOAD_DWORDX16 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x19
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define void @v16i32_arg(<16 x i32> addrspace(1)* nocapture %out, <16 x i32> %in) nounwind {
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entry:
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store <16 x i32> %in, <16 x i32> addrspace(1)* %out, align 4
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ret void
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}
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; EG-CHECK-LABEL: @v16f32_arg
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Y
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Z
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].W
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].X
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Y
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Z
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].W
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].X
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Y
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Z
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].W
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].X
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Y
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Z
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].W
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; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X
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; SI-CHECK-LABEL: @v16f32_arg
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; SI-CHECK: S_LOAD_DWORDX16 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x19
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define void @v16f32_arg(<16 x float> addrspace(1)* nocapture %out, <16 x float> %in) nounwind {
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entry:
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store <16 x float> %in, <16 x float> addrspace(1)* %out, align 4
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ret void
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}
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