mirror of
https://github.com/c64scene-ar/llvm-6502.git
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bec5c611e1
Print in decimal for inline immediates, and hex otherwise. Use hex always for offsets in addressing offsets. This approximately matches what the shader compiler does. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206335 91177308-0d34-0410-b5e6-96231b3b80d8
130 lines
4.5 KiB
LLVM
130 lines
4.5 KiB
LLVM
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s
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;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI %s
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; EG-LABEL: @or_v2i32
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; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; SI-LABEL: @or_v2i32
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; SI: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define void @or_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
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%a = load <2 x i32> addrspace(1) * %in
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%b = load <2 x i32> addrspace(1) * %b_ptr
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%result = or <2 x i32> %a, %b
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store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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ret void
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}
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; EG-LABEL: @or_v4i32
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; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; SI-LABEL: @or_v4i32
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; SI: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define void @or_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
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%a = load <4 x i32> addrspace(1) * %in
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%b = load <4 x i32> addrspace(1) * %b_ptr
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%result = or <4 x i32> %a, %b
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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; SI-LABEL: @scalar_or_i32
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; SI: S_OR_B32
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define void @scalar_or_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) {
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%or = or i32 %a, %b
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store i32 %or, i32 addrspace(1)* %out
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ret void
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}
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; SI-LABEL: @vector_or_i32
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; SI: V_OR_B32_e32 v{{[0-9]}}
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define void @vector_or_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 %b) {
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%loada = load i32 addrspace(1)* %a
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%or = or i32 %loada, %b
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store i32 %or, i32 addrspace(1)* %out
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ret void
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}
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; EG-LABEL: @scalar_or_i64
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; EG-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y
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; EG-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z
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; SI-LABEL: @scalar_or_i64
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; SI: S_OR_B64
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define void @scalar_or_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
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%or = or i64 %a, %b
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store i64 %or, i64 addrspace(1)* %out
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ret void
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}
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; SI-LABEL: @vector_or_i64
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; SI: V_OR_B32_e32 v{{[0-9]}}
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; SI: V_OR_B32_e32 v{{[0-9]}}
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define void @vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
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%loada = load i64 addrspace(1)* %a, align 8
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%loadb = load i64 addrspace(1)* %a, align 8
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%or = or i64 %loada, %loadb
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store i64 %or, i64 addrspace(1)* %out
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ret void
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}
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; SI-LABEL: @scalar_vector_or_i64
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; SI: V_OR_B32_e32 v{{[0-9]}}
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; SI: V_OR_B32_e32 v{{[0-9]}}
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define void @scalar_vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 %b) {
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%loada = load i64 addrspace(1)* %a
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%or = or i64 %loada, %b
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store i64 %or, i64 addrspace(1)* %out
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ret void
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}
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; SI-LABEL: @vector_or_i64_loadimm
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; SI-DAG: S_MOV_B32 [[LO_S_IMM:s[0-9]+]], 0xdf77987f
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; SI-DAG: S_MOV_B32 [[HI_S_IMM:s[0-9]+]], 0x146f
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; SI-DAG: BUFFER_LOAD_DWORDX2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}},
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; SI-DAG: V_OR_B32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
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; SI-DAG: V_OR_B32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
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; SI: S_ENDPGM
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define void @vector_or_i64_loadimm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
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%loada = load i64 addrspace(1)* %a, align 8
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%or = or i64 %loada, 22470723082367
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store i64 %or, i64 addrspace(1)* %out
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ret void
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}
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; FIXME: The or 0 should really be removed.
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; SI-LABEL: @vector_or_i64_imm
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; SI: BUFFER_LOAD_DWORDX2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}},
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; SI: V_OR_B32_e32 {{v[0-9]+}}, 8, v[[LO_VREG]]
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; SI: V_OR_B32_e32 {{v[0-9]+}}, 0, {{.*}}
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; SI: S_ENDPGM
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define void @vector_or_i64_imm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
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%loada = load i64 addrspace(1)* %a, align 8
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%or = or i64 %loada, 8
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store i64 %or, i64 addrspace(1)* %out
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ret void
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}
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; SI-LABEL: @trunc_i64_or_to_i32
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; SI: S_LOAD_DWORD [[SREG0:s[0-9]+]],
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; SI: S_LOAD_DWORD [[SREG1:s[0-9]+]],
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; SI: S_OR_B32 [[SRESULT:s[0-9]+]], [[SREG1]], [[SREG0]]
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; SI: V_MOV_B32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
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; SI: BUFFER_STORE_DWORD [[VRESULT]],
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define void @trunc_i64_or_to_i32(i32 addrspace(1)* %out, i64 %a, i64 %b) {
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%add = or i64 %b, %a
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%trunc = trunc i64 %add to i32
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store i32 %trunc, i32 addrspace(1)* %out, align 8
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ret void
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}
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