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https://github.com/c64scene-ar/llvm-6502.git
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62b9c33e13
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226681 91177308-0d34-0410-b5e6-96231b3b80d8
121 lines
3.2 KiB
LLVM
121 lines
3.2 KiB
LLVM
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
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; Verify that the mpy intrinsics with add/subtract are being lowered to the right instruction.
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@c = external global i64
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; CHECK: r{{[0-9]+}}{{ *}}+{{ *}}={{ *}}mpyi(r{{[0-9]+}}{{ *}},{{ *}}#124)
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define void @test1(i32 %a) #0 {
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entry:
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%0 = load i64* @c, align 8
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%conv = trunc i64 %0 to i32
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%1 = tail call i32 @llvm.hexagon.M2.macsip(i32 %conv, i32 %a, i32 124)
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%conv1 = sext i32 %1 to i64
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store i64 %conv1, i64* @c, align 8
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ret void
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}
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declare i32 @llvm.hexagon.M2.macsip(i32, i32, i32) #1
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; CHECK: r{{[0-9]+}}{{ *}}-{{ *}}={{ *}}mpyi(r{{[0-9]+}}{{ *}},{{ *}}#166)
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define void @test2(i32 %a) #0 {
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entry:
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%0 = load i64* @c, align 8
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%conv = trunc i64 %0 to i32
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%1 = tail call i32 @llvm.hexagon.M2.macsin(i32 %conv, i32 %a, i32 166)
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%conv1 = sext i32 %1 to i64
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store i64 %conv1, i64* @c, align 8
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ret void
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}
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declare i32 @llvm.hexagon.M2.macsin(i32, i32, i32) #1
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; CHECK: r{{[0-9]+}}{{ *}}+{{ *}}={{ *}}mpyi(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}})
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define void @test3(i32 %a, i32 %b) #0 {
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entry:
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%0 = load i64* @c, align 8
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%conv = trunc i64 %0 to i32
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%1 = tail call i32 @llvm.hexagon.M2.maci(i32 %conv, i32 %a, i32 %b)
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%conv1 = sext i32 %1 to i64
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store i64 %conv1, i64* @c, align 8
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ret void
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}
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declare i32 @llvm.hexagon.M2.maci(i32, i32, i32) #1
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@d = external global i32
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; CHECK: r{{[0-9]+}}{{ *}}+{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}#40)
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define void @test7(i32 %a) #0 {
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entry:
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%0 = load i64* @c, align 8
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%conv = trunc i64 %0 to i32
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%1 = tail call i32 @llvm.hexagon.M2.accii(i32 %conv, i32 %a, i32 40)
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%conv1 = sext i32 %1 to i64
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store i64 %conv1, i64* @c, align 8
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ret void
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}
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declare i32 @llvm.hexagon.M2.accii(i32, i32, i32) #1
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; CHECK: r{{[0-9]+}}{{ *}}-{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}#100)
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define void @test8(i32 %a) #0 {
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entry:
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%0 = load i64* @c, align 8
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%conv = trunc i64 %0 to i32
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%1 = tail call i32 @llvm.hexagon.M2.naccii(i32 %conv, i32 %a, i32 100)
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%conv1 = sext i32 %1 to i64
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store i64 %conv1, i64* @c, align 8
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ret void
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}
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declare i32 @llvm.hexagon.M2.naccii(i32, i32, i32) #1
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; CHECK: r{{[0-9]+}}{{ *}}+{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}})
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define void @test9(i32 %a, i32 %b) #0 {
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entry:
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%0 = load i64* @c, align 8
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%conv = trunc i64 %0 to i32
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%1 = tail call i32 @llvm.hexagon.M2.acci(i32 %conv, i32 %a, i32 %b)
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%conv1 = sext i32 %1 to i64
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store i64 %conv1, i64* @c, align 8
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ret void
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}
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declare i32 @llvm.hexagon.M2.acci(i32, i32, i32) #1
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; CHECK: r{{[0-9]+}}{{ *}}+{{ *}}={{ *}}sub(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}})
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define void @test10(i32 %a, i32 %b) #0 {
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entry:
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%0 = load i64* @c, align 8
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%conv = trunc i64 %0 to i32
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%1 = tail call i32 @llvm.hexagon.M2.subacc(i32 %conv, i32 %a, i32 %b)
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%conv1 = sext i32 %1 to i64
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store i64 %conv1, i64* @c, align 8
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ret void
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}
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declare i32 @llvm.hexagon.M2.subacc(i32, i32, i32) #1
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; CHECK: r{{[0-9]+}}{{ *}}-{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}})
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define void @test11(i32 %a, i32 %b) #0 {
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entry:
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%0 = load i64* @c, align 8
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%conv = trunc i64 %0 to i32
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%1 = tail call i32 @llvm.hexagon.M2.nacci(i32 %conv, i32 %a, i32 %b)
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%conv1 = sext i32 %1 to i64
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store i64 %conv1, i64* @c, align 8
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ret void
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}
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declare i32 @llvm.hexagon.M2.nacci(i32, i32, i32) #1
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