mirror of
https://github.com/c64scene-ar/llvm-6502.git
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6d4b270e38
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76062 91177308-0d34-0410-b5e6-96231b3b80d8
128 lines
3.8 KiB
TableGen
128 lines
3.8 KiB
TableGen
//===- SystemZInstrFormats.td - SystemZ Instruction Formats ----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// Format specifies the encoding used by the instruction. This is part of the
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// ad-hoc solution used to emit machine instruction encodings by our machine
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// code emitter.
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class Format<bits<5> val> {
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bits<5> Value = val;
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}
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def Pseudo : Format<0>;
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def EForm : Format<1>;
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def IForm : Format<2>;
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def RIForm : Format<3>;
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def RIEForm : Format<4>;
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def RILForm : Format<5>;
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def RISForm : Format<6>;
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def RRForm : Format<7>;
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def RREForm : Format<8>;
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def RRFForm : Format<9>;
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def RRRForm : Format<10>;
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def RRSForm : Format<11>;
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def RSForm : Format<12>;
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def RSIForm : Format<13>;
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def RSILForm : Format<14>;
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def RSYForm : Format<15>;
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def RXForm : Format<16>;
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def RXEForm : Format<17>;
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def RXFForm : Format<18>;
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def RXYForm : Format<19>;
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def SForm : Format<20>;
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def SIForm : Format<21>;
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def SILForm : Format<22>;
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def SIYForm : Format<23>;
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def SSForm : Format<24>;
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def SSEForm : Format<25>;
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def SSFForm : Format<26>;
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class InstSystemZ<bits<16> op, Format f, dag outs, dag ins> : Instruction {
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let Namespace = "SystemZ";
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bits<16> Opcode = op;
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Format Form = f;
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bits<5> FormBits = Form.Value;
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dag OutOperandList = outs;
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dag InOperandList = ins;
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}
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class I8<bits<8> op, Format f, dag outs, dag ins, string asmstr,
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list<dag> pattern>
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: InstSystemZ<0, f, outs, ins> {
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let Opcode{0-7} = op;
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let Opcode{8-15} = 0;
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let Pattern = pattern;
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let AsmString = asmstr;
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}
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class I12<bits<12> op, Format f, dag outs, dag ins, string asmstr,
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list<dag> pattern>
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: InstSystemZ<0, f, outs, ins> {
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let Opcode{0-11} = op;
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let Opcode{12-15} = 0;
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let Pattern = pattern;
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let AsmString = asmstr;
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}
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class I16<bits<16> op, Format f, dag outs, dag ins, string asmstr,
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list<dag> pattern>
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: InstSystemZ<op, f, outs, ins> {
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let Pattern = pattern;
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let AsmString = asmstr;
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}
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class RRI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: I8<op, RRForm, outs, ins, asmstr, pattern>;
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class RII<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: I12<op, RIForm, outs, ins, asmstr, pattern>;
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class RILI<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: I12<op, RILForm, outs, ins, asmstr, pattern>;
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class RREI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: I16<op, RREForm, outs, ins, asmstr, pattern>;
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class RXI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: I8<op, RXForm, outs, ins, asmstr, pattern>;
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class RXYI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: I16<op, RXYForm, outs, ins, asmstr, pattern>;
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class RSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: I8<op, RSForm, outs, ins, asmstr, pattern>;
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class RSYI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: I16<op, RSYForm, outs, ins, asmstr, pattern>;
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class SII<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: I8<op, SIForm, outs, ins, asmstr, pattern>;
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class SIYI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: I16<op, SIYForm, outs, ins, asmstr, pattern>;
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class SILI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: I16<op, SILForm, outs, ins, asmstr, pattern>;
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//===----------------------------------------------------------------------===//
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// Pseudo instructions
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//===----------------------------------------------------------------------===//
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class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<0, Pseudo, outs, ins> {
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let Pattern = pattern;
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let AsmString = asmstr;
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}
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