Tim Northover e43c5023fe ARM: teach AAPCS-VFP to deal with Cortex-M4. ... Cortex-M4 only has single-precision floating point support, so any LLVM "double" type will have been split into 2 i32s by now. Fortunately, the consecutive-register framework turns out to be precisely what's needed to reconstruct the double and follow AAPCS-VFP correctly! rdar://problem/17012966 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209650 91177308-0d34-0410-b5e6-96231b3b80d8		2014-05-27 10:43:38 +00:00
..
AArch64	AArch64: force i1 to be zero-extended at an ABI boundary.	2014-05-26 17:22:07 +00:00
ARM	ARM: teach AAPCS-VFP to deal with Cortex-M4.	2014-05-27 10:43:38 +00:00
CPP
Generic
Hexagon
Inputs
Mips	Use alias linkage and visibility to decide tls access mode.	2014-05-23 19:16:56 +00:00
MSP430	Fix broken FileCheck prefixes	2014-05-23 19:06:24 +00:00
NVPTX
PowerPC	[PPC] Use alias symbols in address computation.	2014-05-26 19:08:19 +00:00
R600	R600: Try to convert BFE back to standard bit ops when possible.	2014-05-22 18:09:12 +00:00
SPARC
SystemZ
Thumb	Segmented stacks: omit __morestack call when there's no frame.	2014-05-22 13:03:43 +00:00
Thumb2
X86	Convert some X86 blendv* intrinsics into IR.	2014-05-27 03:42:20 +00:00
XCore