Hal Finkel d715c3e9ac Add support for positionally-encoded operands to FixedLenDecoderEmitter ... Unfortunately, the PowerPC instruction definitions make heavy use of the positional operand encoding heuristic to map operands onto bitfield variables in the instruction definitions. Changing this to use name-based mapping is not trivial, however, because additional infrastructure needs to be designed to handle mapping of complex operands (with multiple suboperands) onto multiple bitfield variables. In the mean time, this adds support for positionally encoded operands to FixedLenDecoderEmitter, so that we can generate a disassembler for the PowerPC backend. To prevent an accidental reliance on this feature, and to prevent an undesirable interaction with existing disassemblers, a backend must opt-in to this support by setting the new decodePositionallyEncodedOperands instruction-set bit to true. When enabled, this iterates the variables that contribute to the instruction encoding, just as the encoder does, and emulates the procedure the encoder uses to map "numbered" operands to variables. The bit range for each variable is also determined as the encoder determines them. This map is then consulted during the decoder-generator's loop over operands to decode, allowing the decoder to understand both position-based and name-based operand-to-variable mappings. As noted in the comment on the decodePositionallyEncodedOperands definition, this support should be removed once it is no longer needed. There should be no change to existing disassemblers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197691 91177308-0d34-0410-b5e6-96231b3b80d8		2013-12-19 16:12:53 +00:00
..
CostTable.h	Add a overload to CostTable which allows it to infer the size of the table.	2013-08-09 19:33:32 +00:00
Mangler.h	Remove the isImplicitlyPrivate argument of getNameWithPrefix.	2013-12-05 05:53:12 +00:00
Target.td	Add support for positionally-encoded operands to FixedLenDecoderEmitter	2013-12-19 16:12:53 +00:00
TargetCallingConv.h	SelectionDAG: Pass along the original argument/element type in ISD::InputArg	2013-10-23 00:44:24 +00:00
TargetCallingConv.td	Add an OtherPreserved field to the CalleeSaved TableGen class.	2013-08-23 02:25:47 +00:00
TargetFrameLowering.h	[SystemZ] Clean up register scavenging code	2013-07-05 12:55:00 +00:00
TargetInstrInfo.h	Added a size field to the stack map record to handle subregister spills.	2013-11-17 01:36:23 +00:00
TargetIntrinsicInfo.h	Mark unimplemented copy constructors and copy assignment operators as LLVM_DELETED_FUNCTION.	2012-09-17 06:59:23 +00:00
TargetItinerary.td	I'm introducing a new machine model to simultaneously allow simple	2012-07-07 04:00:00 +00:00
TargetJITInfo.h	Sort the #include lines for the include/... tree with the script.	2012-12-03 17:02:12 +00:00
TargetLibraryInfo.h	Enable double to float shrinking optimizations for binary functions like 'fmin/fmax'. Fix radar:15283121	2013-12-16 22:42:40 +00:00
TargetLowering.h	Add TargetLowering::prepareVolatileOrAtomicLoad	2013-12-10 10:36:34 +00:00
TargetLoweringObjectFile.h	Move getSymbolWithGlobalValueBase to TargetLoweringObjectFile.	2013-12-02 16:25:47 +00:00
TargetMachine.h	Add a RequireStructuredCFG Field to TargetMachine.	2013-12-07 01:49:19 +00:00
TargetOpcodes.h	Lower stackmap intrinsics directly to their target opcode in the DAG builder.	2013-10-31 17:18:24 +00:00
TargetOptions.h	Use function attributes to indicate that we don't want to realign the stack.	2013-08-01 21:42:05 +00:00
TargetRegisterInfo.h	Add TargetRegisterInfo::reverseLocalAssignment hook.	2013-12-11 03:40:15 +00:00
TargetSchedule.td	Machine model comments. Explain a ProcessorUnit's BufferSize.	2013-12-05 17:55:53 +00:00
TargetSelectionDAG.td	Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instructions:	2013-09-04 09:28:24 +00:00
TargetSelectionDAGInfo.h	[SystemZ] Use SRST to optimize memchr	2013-08-20 09:38:48 +00:00
TargetSubtargetInfo.h	Added temp flag -misched-bench for staging in default changes.	2013-09-26 05:53:35 +00:00