Tim Northover f8c7bd4696 ARM64: merge "extend" and "shift" addressing-mode enums. ...

In terms of assembly, these have too much overlap to be neatly modelled as
disjoint classes: in many cases "lsl" is an acceptable alternative to either
"uxtw" or "uxtx".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208563 91177308-0d34-0410-b5e6-96231b3b80d8

2014-05-12 14:13:17 +00:00

..

AsmParser

ARM64: merge "extend" and "shift" addressing-mode enums.

2014-05-12 14:13:17 +00:00

Disassembler

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InstPrinter

ARM64: merge "extend" and "shift" addressing-mode enums.

2014-05-12 14:13:17 +00:00

MCTargetDesc

ARM64: merge "extend" and "shift" addressing-mode enums.

2014-05-12 14:13:17 +00:00

TargetInfo

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Utils

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ARM64.h

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ARM64.td

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ARM64AddressTypePromotion.cpp

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ARM64AdvSIMDScalarPass.cpp

[ARM64][fast-isel] Disable target specific optimizations at -O0. Functionally,

2014-05-07 16:41:55 +00:00

ARM64AsmPrinter.cpp

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ARM64BranchRelaxation.cpp

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ARM64CallingConv.h

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ARM64CallingConvention.td

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ARM64CleanupLocalDynamicTLSPass.cpp

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ARM64CollectLOH.cpp

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ARM64ConditionalCompares.cpp

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ARM64DeadRegisterDefinitionsPass.cpp

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ARM64ExpandPseudoInsts.cpp

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ARM64FastISel.cpp

[ARM64-BE] Teach fast-isel about how to set up sub-word stack arguments for big endian calls.

2014-05-08 12:53:50 +00:00

ARM64FrameLowering.cpp

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ARM64FrameLowering.h

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ARM64InstrAtomics.td

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ARM64InstrFormats.td

ARM64: merge "extend" and "shift" addressing-mode enums.

2014-05-12 14:13:17 +00:00

ARM64InstrInfo.cpp

ARM64: merge "extend" and "shift" addressing-mode enums.

2014-05-12 14:13:17 +00:00

ARM64InstrInfo.h

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ARM64InstrInfo.td

[ARM64] Add proper bounds checking/diagnostics to logical shifts

2014-05-12 11:49:16 +00:00

ARM64ISelDAGToDAG.cpp

ARM64: merge "extend" and "shift" addressing-mode enums.

2014-05-12 14:13:17 +00:00

ARM64ISelLowering.cpp

Pass the value type to TLI::getRegisterByName

2014-05-11 19:29:07 +00:00

ARM64ISelLowering.h

Pass the value type to TLI::getRegisterByName

2014-05-11 19:29:07 +00:00

ARM64LoadStoreOptimizer.cpp

[ARM64][fast-isel] Disable target specific optimizations at -O0. Functionally,

2014-05-07 16:41:55 +00:00

ARM64MachineFunctionInfo.h

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ARM64MCInstLower.cpp

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ARM64MCInstLower.h

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ARM64PerfectShuffle.h

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ARM64PromoteConstant.cpp

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ARM64RegisterInfo.cpp

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ARM64RegisterInfo.h

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ARM64RegisterInfo.td

[ARM64] Move register/register MOV handling into tablegen and improve diagnostics

2014-05-12 09:38:16 +00:00

ARM64SchedA53.td

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ARM64SchedCyclone.td

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ARM64Schedule.td

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ARM64SelectionDAGInfo.cpp

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ARM64SelectionDAGInfo.h

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ARM64StorePairSuppress.cpp

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ARM64Subtarget.cpp

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ARM64Subtarget.h

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ARM64TargetMachine.cpp

[ARM64][fast-isel] Disable target specific optimizations at -O0. Functionally,

2014-05-07 16:41:55 +00:00

ARM64TargetMachine.h

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ARM64TargetObjectFile.cpp

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ARM64TargetObjectFile.h

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ARM64TargetTransformInfo.cpp

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CMakeLists.txt

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LLVMBuild.txt

Fix broken build

2014-05-09 18:06:22 +00:00

Makefile

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