Vincent Lejeune f7c9b95f94 R600: PV stores Reg id, not index ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184117 91177308-0d34-0410-b5e6-96231b3b80d8		2013-06-17 20:16:40 +00:00
..
AArch64	Change how we iterate over relocations on ELF.	2013-05-30 03:05:14 +00:00
ARM	Switch spill weights from a basic loop depth estimation to BlockFrequencyInfo.	2013-06-17 19:00:36 +00:00
CPP
Generic	Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen.	2013-05-21 14:37:16 +00:00
Hexagon	Hexagon: Pass to replace tranfer/copy instructions into combine instruction	2013-05-14 18:54:06 +00:00
Inputs
MBlaze
Mips	[mips] Add an IR transformation pass that optimizes calls to sqrt.	2013-06-11 22:21:44 +00:00
MSP430
NVPTX	[NVPTX] Remove old CONST_NOT_GEN address space that is not being used anymore and causes constants to be emitted in the global address space	2013-06-10 13:29:47 +00:00
PowerPC	[PowerPC] Disable fast-isel for existing -O0 tests for PowerPC.	2013-06-13 20:23:34 +00:00
R600	R600: PV stores Reg id, not index	2013-06-17 20:16:40 +00:00
SI
SPARC	Switch spill weights from a basic loop depth estimation to BlockFrequencyInfo.	2013-06-17 19:00:36 +00:00
SystemZ	[SystemZ] Don't use LOAD and STORE REVERSED for volatile accesses	2013-05-31 13:25:22 +00:00
Thumb
Thumb2	Cortex-R5 can issue Thumb2 integer division instructions.	2013-06-04 22:52:09 +00:00
X86	Switch spill weights from a basic loop depth estimation to BlockFrequencyInfo.	2013-06-17 19:00:36 +00:00
XCore