Jakob Stoklund Olesen 2622f4622c When isel is emitting instructions for an x86 target without CMOV, the CFG is ... edited during emission. If the basic block ends in a switch that gets lowered to a jump table, any phis at the default edge were getting updated wrong. The jump table data structure keeps a pointer to the header blocks that wasn't getting updated after the MBB is split. This bug was exposed on 32-bit Linux when disabling critical edge splitting in codegen prepare. The fix is to uipdate stale MBB pointers whenever a block is split during emission. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115191 91177308-0d34-0410-b5e6-96231b3b80d8		2010-09-30 19:44:31 +00:00
..
Alpha
ARM	Tiny patch for proof-of-concept cleanup of ARMAsmPrinter::EmitStartOfAsmFile()	2010-09-30 02:45:56 +00:00
Blackfin
CBackend
CellSPU	Change SPU register re-interpretations from OR to COPY_TO_REGCLASS instruction.	2010-09-16 12:29:33 +00:00
CPP
Generic
MBlaze
Mips	Enable machine sinking critical edge splitting. e.g.	2010-09-20 22:52:00 +00:00
MSP430	CombinerAA is now reordering these stores.	2010-09-20 20:56:29 +00:00
PIC16
PowerPC	the latest assembler that runs on powerpc 10.4 machines doesn't	2010-09-27 06:44:54 +00:00
PTX	Add test case for PTX ret instruction	2010-09-25 07:49:54 +00:00
SPARC
SystemZ	Correct bogus module triple specifications.	2010-08-30 10:48:29 +00:00
Thumb	Revert "Disable codegen prepare critical edge splitting. Machine instruction passes now"	2010-09-27 18:43:48 +00:00
Thumb2	Enable target-specific mul-lowering on ARM, even at -Os. Remove a test that this makes	2010-09-21 22:51:46 +00:00
X86	When isel is emitting instructions for an x86 target without CMOV, the CFG is	2010-09-30 19:44:31 +00:00
XCore	Enable machine sinking critical edge splitting. e.g.	2010-09-20 22:52:00 +00:00
thumb2-mul.ll	Enable target-specific mul-lowering on ARM, even at -Os. Remove a test that this makes	2010-09-21 22:51:46 +00:00