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https://github.com/c64scene-ar/llvm-6502.git
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f99998a2b0
Previously mips16 was sharing the pattern addr which is used for mips32 and mips64. This had a number of problems: 1) Storing and loading byte and halfword quantities for mips16 has particular problems due to the primarily non mips16 nature of SP. When we must load/store byte/halfword stack objects in a function, we must create a mips16 alias register for SP. This functionality is tested in stchar.ll. 2) We need to have an FP register under certain conditions (such as dynamically sized alloca). We use mips16 register S0 for this purpose. In this case, we also use this register when accessing frame objects so this issue also affects the complex pattern addr16. This functionality is tested in alloca16.ll. The Mips16InstrInfo.td has been updated to use addr16 instead of addr. The complex pattern C++ function for addr has been copied to addr16 and updated to reflect the above issues. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166897 91177308-0d34-0410-b5e6-96231b3b80d8 |
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| CellSPU | ||
| CPP | ||
| Generic | ||
| Hexagon | ||
| MBlaze | ||
| Mips | ||
| MSP430 | ||
| NVPTX | ||
| PowerPC | ||
| SPARC | ||
| Thumb | ||
| Thumb2 | ||
| X86 | ||
| XCore | ||