Weiming Zhao fa1cf8cd68 [ARM64] Prevent bit extraction to be adjusted by following shift ... For pattern like ((x >> C1) & Mask) << C2, DAG combiner may convert it into (x >> (C1-C2)) & (Mask << C2), which makes pattern matching of ubfx more difficult. For example: Given %shr = lshr i64 %x, 4 %and = and i64 %shr, 15 %arrayidx = getelementptr inbounds [8 x [64 x i64]]* @arr, i64 0, %i64 2, i64 %and %0 = load i64* %arrayidx With current shift folding, it takes 3 instrs to compute base address: lsr x8, x0, #1 and x8, x8, #0x78 add x8, x9, x8 If using ubfx, it only needs 2 instrs: ubfx x8, x0, #4, #4 add x8, x9, x8, lsl #3 This fixes bug 19589 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207702 91177308-0d34-0410-b5e6-96231b3b80d8		2014-04-30 21:07:24 +00:00
..
CostTable.h
Target.td
TargetCallingConv.h
TargetCallingConv.td
TargetFrameLowering.h	[C++11] More 'nullptr' conversion. In some cases just using a boolean check instead of comparing to nullptr.	2014-04-14 00:51:57 +00:00
TargetInstrInfo.h	[C++11] More 'nullptr' conversion. In some cases just using a boolean check instead of comparing to nullptr.	2014-04-14 00:51:57 +00:00
TargetIntrinsicInfo.h	[C++11] More 'nullptr' conversion. In some cases just using a boolean check instead of comparing to nullptr.	2014-04-15 06:32:26 +00:00
TargetItinerary.td
TargetJITInfo.h
TargetLibraryInfo.h
TargetLowering.h	[ARM64] Prevent bit extraction to be adjusted by following shift	2014-04-30 21:07:24 +00:00
TargetLoweringObjectFile.h	[C++11] More 'nullptr' conversion. In some cases just using a boolean check instead of comparing to nullptr.	2014-04-14 00:51:57 +00:00
TargetMachine.h	Fix comment	2014-04-28 18:11:51 +00:00
TargetOpcodes.h
TargetOptions.h	Create MCTargetOptions.	2014-04-23 11:16:03 +00:00
TargetRegisterInfo.h	[C++11] More 'nullptr' conversion. In some cases just using a boolean check instead of comparing to nullptr.	2014-04-14 00:51:57 +00:00
TargetSchedule.td
TargetSelectionDAG.td
TargetSelectionDAGInfo.h
TargetSubtargetInfo.h