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is faster and is needed for future improvements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30383 91177308-0d34-0410-b5e6-96231b3b80d8
1338 lines
52 KiB
C++
1338 lines
52 KiB
C++
//===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the LiveInterval analysis pass which is used
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// by the Linear Scan Register allocator. This pass linearizes the
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// basic blocks of the function in DFS order and uses the
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// LiveVariables pass to conservatively compute live intervals for
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// each virtual and physical register.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "liveintervals"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "VirtRegMap.h"
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#include "llvm/Value.h"
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#include "llvm/Analysis/LoopInfo.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/MRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/STLExtras.h"
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#include <algorithm>
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#include <cmath>
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#include <iostream>
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using namespace llvm;
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namespace {
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RegisterPass<LiveIntervals> X("liveintervals", "Live Interval Analysis");
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static Statistic<> numIntervals
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("liveintervals", "Number of original intervals");
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static Statistic<> numIntervalsAfter
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("liveintervals", "Number of intervals after coalescing");
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static Statistic<> numJoins
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("liveintervals", "Number of interval joins performed");
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static Statistic<> numPeep
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("liveintervals", "Number of identity moves eliminated after coalescing");
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static Statistic<> numFolded
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("liveintervals", "Number of loads/stores folded into instructions");
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static cl::opt<bool>
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EnableJoining("join-liveintervals",
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cl::desc("Coallesce copies (default=true)"),
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cl::init(true));
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}
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void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<LiveVariables>();
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AU.addPreservedID(PHIEliminationID);
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AU.addRequiredID(PHIEliminationID);
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AU.addRequiredID(TwoAddressInstructionPassID);
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AU.addRequired<LoopInfo>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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void LiveIntervals::releaseMemory() {
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mi2iMap_.clear();
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i2miMap_.clear();
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r2iMap_.clear();
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r2rMap_.clear();
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}
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static bool isZeroLengthInterval(LiveInterval *li) {
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for (LiveInterval::Ranges::const_iterator
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i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
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if (i->end - i->start > LiveIntervals::InstrSlots::NUM)
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return false;
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return true;
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}
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/// runOnMachineFunction - Register allocate the whole function
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///
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bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
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mf_ = &fn;
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tm_ = &fn.getTarget();
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mri_ = tm_->getRegisterInfo();
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tii_ = tm_->getInstrInfo();
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lv_ = &getAnalysis<LiveVariables>();
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allocatableRegs_ = mri_->getAllocatableSet(fn);
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r2rMap_.grow(mf_->getSSARegMap()->getLastVirtReg());
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// If this function has any live ins, insert a dummy instruction at the
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// beginning of the function that we will pretend "defines" the values. This
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// is to make the interval analysis simpler by providing a number.
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if (fn.livein_begin() != fn.livein_end()) {
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unsigned FirstLiveIn = fn.livein_begin()->first;
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// Find a reg class that contains this live in.
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const TargetRegisterClass *RC = 0;
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for (MRegisterInfo::regclass_iterator RCI = mri_->regclass_begin(),
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E = mri_->regclass_end(); RCI != E; ++RCI)
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if ((*RCI)->contains(FirstLiveIn)) {
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RC = *RCI;
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break;
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}
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MachineInstr *OldFirstMI = fn.begin()->begin();
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mri_->copyRegToReg(*fn.begin(), fn.begin()->begin(),
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FirstLiveIn, FirstLiveIn, RC);
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assert(OldFirstMI != fn.begin()->begin() &&
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"copyRetToReg didn't insert anything!");
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}
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// Number MachineInstrs and MachineBasicBlocks.
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// Initialize MBB indexes to a sentinal.
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MBB2IdxMap.resize(mf_->getNumBlockIDs(), ~0U);
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unsigned MIIndex = 0;
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for (MachineFunction::iterator MBB = mf_->begin(), E = mf_->end();
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MBB != E; ++MBB) {
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// Set the MBB2IdxMap entry for this MBB.
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MBB2IdxMap[MBB->getNumber()] = MIIndex;
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for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
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I != E; ++I) {
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bool inserted = mi2iMap_.insert(std::make_pair(I, MIIndex)).second;
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assert(inserted && "multiple MachineInstr -> index mappings");
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i2miMap_.push_back(I);
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MIIndex += InstrSlots::NUM;
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}
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}
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// Note intervals due to live-in values.
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if (fn.livein_begin() != fn.livein_end()) {
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MachineBasicBlock *Entry = fn.begin();
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for (MachineFunction::livein_iterator I = fn.livein_begin(),
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E = fn.livein_end(); I != E; ++I) {
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handlePhysicalRegisterDef(Entry, Entry->begin(), 0,
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getOrCreateInterval(I->first), 0);
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for (const unsigned* AS = mri_->getAliasSet(I->first); *AS; ++AS)
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handlePhysicalRegisterDef(Entry, Entry->begin(), 0,
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getOrCreateInterval(*AS), 0);
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}
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}
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computeIntervals();
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numIntervals += getNumIntervals();
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DEBUG(std::cerr << "********** INTERVALS **********\n";
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for (iterator I = begin(), E = end(); I != E; ++I) {
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I->second.print(std::cerr, mri_);
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std::cerr << "\n";
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});
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// Join (coallesce) intervals if requested.
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if (EnableJoining) joinIntervals();
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numIntervalsAfter += getNumIntervals();
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// perform a final pass over the instructions and compute spill
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// weights, coalesce virtual registers and remove identity moves.
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const LoopInfo &loopInfo = getAnalysis<LoopInfo>();
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for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
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mbbi != mbbe; ++mbbi) {
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MachineBasicBlock* mbb = mbbi;
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unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock());
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for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
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mii != mie; ) {
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// if the move will be an identity move delete it
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unsigned srcReg, dstReg, RegRep;
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if (tii_->isMoveInstr(*mii, srcReg, dstReg) &&
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(RegRep = rep(srcReg)) == rep(dstReg)) {
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// remove from def list
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LiveInterval &interval = getOrCreateInterval(RegRep);
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RemoveMachineInstrFromMaps(mii);
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mii = mbbi->erase(mii);
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++numPeep;
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}
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else {
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for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) {
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const MachineOperand &mop = mii->getOperand(i);
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if (mop.isRegister() && mop.getReg() &&
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MRegisterInfo::isVirtualRegister(mop.getReg())) {
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// replace register with representative register
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unsigned reg = rep(mop.getReg());
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mii->getOperand(i).setReg(reg);
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LiveInterval &RegInt = getInterval(reg);
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RegInt.weight +=
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(mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth);
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}
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}
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++mii;
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}
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}
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}
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for (iterator I = begin(), E = end(); I != E; ++I) {
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LiveInterval &li = I->second;
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if (MRegisterInfo::isVirtualRegister(li.reg)) {
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// If the live interval length is essentially zero, i.e. in every live
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// range the use follows def immediately, it doesn't make sense to spill
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// it and hope it will be easier to allocate for this li.
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if (isZeroLengthInterval(&li))
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li.weight = float(HUGE_VAL);
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}
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}
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DEBUG(dump());
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return true;
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}
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/// print - Implement the dump method.
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void LiveIntervals::print(std::ostream &O, const Module* ) const {
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O << "********** INTERVALS **********\n";
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for (const_iterator I = begin(), E = end(); I != E; ++I) {
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I->second.print(std::cerr, mri_);
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std::cerr << "\n";
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}
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O << "********** MACHINEINSTRS **********\n";
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for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
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mbbi != mbbe; ++mbbi) {
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O << ((Value*)mbbi->getBasicBlock())->getName() << ":\n";
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for (MachineBasicBlock::iterator mii = mbbi->begin(),
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mie = mbbi->end(); mii != mie; ++mii) {
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O << getInstructionIndex(mii) << '\t' << *mii;
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}
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}
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}
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std::vector<LiveInterval*> LiveIntervals::
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addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) {
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// since this is called after the analysis is done we don't know if
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// LiveVariables is available
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lv_ = getAnalysisToUpdate<LiveVariables>();
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std::vector<LiveInterval*> added;
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assert(li.weight != HUGE_VAL &&
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"attempt to spill already spilled interval!");
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DEBUG(std::cerr << "\t\t\t\tadding intervals for spills for interval: ";
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li.print(std::cerr, mri_); std::cerr << '\n');
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const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg);
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for (LiveInterval::Ranges::const_iterator
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i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) {
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unsigned index = getBaseIndex(i->start);
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unsigned end = getBaseIndex(i->end-1) + InstrSlots::NUM;
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for (; index != end; index += InstrSlots::NUM) {
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// skip deleted instructions
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while (index != end && !getInstructionFromIndex(index))
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index += InstrSlots::NUM;
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if (index == end) break;
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MachineInstr *MI = getInstructionFromIndex(index);
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RestartInstruction:
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for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
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MachineOperand& mop = MI->getOperand(i);
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if (mop.isRegister() && mop.getReg() == li.reg) {
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if (MachineInstr *fmi = mri_->foldMemoryOperand(MI, i, slot)) {
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// Attempt to fold the memory reference into the instruction. If we
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// can do this, we don't need to insert spill code.
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if (lv_)
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lv_->instructionChanged(MI, fmi);
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MachineBasicBlock &MBB = *MI->getParent();
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vrm.virtFolded(li.reg, MI, i, fmi);
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mi2iMap_.erase(MI);
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i2miMap_[index/InstrSlots::NUM] = fmi;
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mi2iMap_[fmi] = index;
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MI = MBB.insert(MBB.erase(MI), fmi);
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++numFolded;
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// Folding the load/store can completely change the instruction in
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// unpredictable ways, rescan it from the beginning.
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goto RestartInstruction;
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} else {
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// Create a new virtual register for the spill interval.
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unsigned NewVReg = mf_->getSSARegMap()->createVirtualRegister(rc);
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// Scan all of the operands of this instruction rewriting operands
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// to use NewVReg instead of li.reg as appropriate. We do this for
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// two reasons:
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//
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// 1. If the instr reads the same spilled vreg multiple times, we
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// want to reuse the NewVReg.
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// 2. If the instr is a two-addr instruction, we are required to
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// keep the src/dst regs pinned.
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//
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// Keep track of whether we replace a use and/or def so that we can
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// create the spill interval with the appropriate range.
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mop.setReg(NewVReg);
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bool HasUse = mop.isUse();
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bool HasDef = mop.isDef();
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for (unsigned j = i+1, e = MI->getNumOperands(); j != e; ++j) {
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if (MI->getOperand(j).isReg() &&
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MI->getOperand(j).getReg() == li.reg) {
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MI->getOperand(j).setReg(NewVReg);
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HasUse |= MI->getOperand(j).isUse();
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HasDef |= MI->getOperand(j).isDef();
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}
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}
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// create a new register for this spill
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vrm.grow();
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vrm.assignVirt2StackSlot(NewVReg, slot);
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LiveInterval &nI = getOrCreateInterval(NewVReg);
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assert(nI.empty());
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// the spill weight is now infinity as it
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// cannot be spilled again
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nI.weight = float(HUGE_VAL);
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if (HasUse) {
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LiveRange LR(getLoadIndex(index), getUseIndex(index),
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nI.getNextValue(~0U, 0));
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DEBUG(std::cerr << " +" << LR);
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nI.addRange(LR);
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}
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if (HasDef) {
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LiveRange LR(getDefIndex(index), getStoreIndex(index),
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nI.getNextValue(~0U, 0));
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DEBUG(std::cerr << " +" << LR);
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nI.addRange(LR);
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}
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added.push_back(&nI);
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// update live variables if it is available
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if (lv_)
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lv_->addVirtualRegisterKilled(NewVReg, MI);
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DEBUG(std::cerr << "\t\t\t\tadded new interval: ";
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nI.print(std::cerr, mri_); std::cerr << '\n');
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}
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}
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}
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}
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}
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return added;
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}
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void LiveIntervals::printRegName(unsigned reg) const {
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if (MRegisterInfo::isPhysicalRegister(reg))
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std::cerr << mri_->getName(reg);
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else
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std::cerr << "%reg" << reg;
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}
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void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
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MachineBasicBlock::iterator mi,
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unsigned MIIdx,
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LiveInterval &interval) {
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DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg));
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LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
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// Virtual registers may be defined multiple times (due to phi
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// elimination and 2-addr elimination). Much of what we do only has to be
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// done once for the vreg. We use an empty interval to detect the first
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// time we see a vreg.
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if (interval.empty()) {
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// Get the Idx of the defining instructions.
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unsigned defIndex = getDefIndex(MIIdx);
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unsigned ValNum;
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unsigned SrcReg, DstReg;
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if (!tii_->isMoveInstr(*mi, SrcReg, DstReg))
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ValNum = interval.getNextValue(~0U, 0);
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else
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ValNum = interval.getNextValue(defIndex, SrcReg);
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assert(ValNum == 0 && "First value in interval is not 0?");
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ValNum = 0; // Clue in the optimizer.
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// Loop over all of the blocks that the vreg is defined in. There are
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// two cases we have to handle here. The most common case is a vreg
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// whose lifetime is contained within a basic block. In this case there
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// will be a single kill, in MBB, which comes after the definition.
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if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
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// FIXME: what about dead vars?
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unsigned killIdx;
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if (vi.Kills[0] != mi)
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killIdx = getUseIndex(getInstructionIndex(vi.Kills[0]))+1;
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else
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killIdx = defIndex+1;
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// If the kill happens after the definition, we have an intra-block
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// live range.
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if (killIdx > defIndex) {
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assert(vi.AliveBlocks.empty() &&
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"Shouldn't be alive across any blocks!");
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LiveRange LR(defIndex, killIdx, ValNum);
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interval.addRange(LR);
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DEBUG(std::cerr << " +" << LR << "\n");
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return;
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}
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}
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// The other case we handle is when a virtual register lives to the end
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// of the defining block, potentially live across some blocks, then is
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// live into some number of blocks, but gets killed. Start by adding a
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// range that goes from this definition to the end of the defining block.
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LiveRange NewLR(defIndex,
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getInstructionIndex(&mbb->back()) + InstrSlots::NUM,
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ValNum);
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DEBUG(std::cerr << " +" << NewLR);
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interval.addRange(NewLR);
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// Iterate over all of the blocks that the variable is completely
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// live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
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// live interval.
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for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) {
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if (vi.AliveBlocks[i]) {
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MachineBasicBlock *MBB = mf_->getBlockNumbered(i);
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if (!MBB->empty()) {
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LiveRange LR(getMBBStartIdx(i),
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getInstructionIndex(&MBB->back()) + InstrSlots::NUM,
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ValNum);
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interval.addRange(LR);
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DEBUG(std::cerr << " +" << LR);
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}
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}
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}
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// Finally, this virtual register is live from the start of any killing
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// block to the 'use' slot of the killing instruction.
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for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
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MachineInstr *Kill = vi.Kills[i];
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LiveRange LR(getMBBStartIdx(Kill->getParent()),
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getUseIndex(getInstructionIndex(Kill))+1,
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ValNum);
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interval.addRange(LR);
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DEBUG(std::cerr << " +" << LR);
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}
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} else {
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// If this is the second time we see a virtual register definition, it
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// must be due to phi elimination or two addr elimination. If this is
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// the result of two address elimination, then the vreg is the first
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// operand, and is a def-and-use.
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if (mi->getOperand(0).isRegister() &&
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mi->getOperand(0).getReg() == interval.reg &&
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mi->getNumOperands() > 1 && mi->getOperand(1).isRegister() &&
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mi->getOperand(1).getReg() == interval.reg &&
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mi->getOperand(0).isDef() && mi->getOperand(1).isUse()) {
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// If this is a two-address definition, then we have already processed
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// the live range. The only problem is that we didn't realize there
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// are actually two values in the live interval. Because of this we
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// need to take the LiveRegion that defines this register and split it
|
|
// into two values.
|
|
unsigned DefIndex = getDefIndex(getInstructionIndex(vi.DefInst));
|
|
unsigned RedefIndex = getDefIndex(MIIdx);
|
|
|
|
// Delete the initial value, which should be short and continuous,
|
|
// because the 2-addr copy must be in the same MBB as the redef.
|
|
interval.removeRange(DefIndex, RedefIndex);
|
|
|
|
// Two-address vregs should always only be redefined once. This means
|
|
// that at this point, there should be exactly one value number in it.
|
|
assert(interval.containsOneValue() && "Unexpected 2-addr liveint!");
|
|
|
|
// The new value number (#1) is defined by the instruction we claimed
|
|
// defined value #0.
|
|
unsigned ValNo = interval.getNextValue(0, 0);
|
|
interval.setValueNumberInfo(1, interval.getValNumInfo(0));
|
|
|
|
// Value#0 is now defined by the 2-addr instruction.
|
|
interval.setValueNumberInfo(0, std::make_pair(~0U, 0U));
|
|
|
|
// Add the new live interval which replaces the range for the input copy.
|
|
LiveRange LR(DefIndex, RedefIndex, ValNo);
|
|
DEBUG(std::cerr << " replace range with " << LR);
|
|
interval.addRange(LR);
|
|
|
|
// If this redefinition is dead, we need to add a dummy unit live
|
|
// range covering the def slot.
|
|
if (lv_->RegisterDefIsDead(mi, interval.reg))
|
|
interval.addRange(LiveRange(RedefIndex, RedefIndex+1, 0));
|
|
|
|
DEBUG(std::cerr << "RESULT: "; interval.print(std::cerr, mri_));
|
|
|
|
} else {
|
|
// Otherwise, this must be because of phi elimination. If this is the
|
|
// first redefinition of the vreg that we have seen, go back and change
|
|
// the live range in the PHI block to be a different value number.
|
|
if (interval.containsOneValue()) {
|
|
assert(vi.Kills.size() == 1 &&
|
|
"PHI elimination vreg should have one kill, the PHI itself!");
|
|
|
|
// Remove the old range that we now know has an incorrect number.
|
|
MachineInstr *Killer = vi.Kills[0];
|
|
unsigned Start = getMBBStartIdx(Killer->getParent());
|
|
unsigned End = getUseIndex(getInstructionIndex(Killer))+1;
|
|
DEBUG(std::cerr << "Removing [" << Start << "," << End << "] from: ";
|
|
interval.print(std::cerr, mri_); std::cerr << "\n");
|
|
interval.removeRange(Start, End);
|
|
DEBUG(std::cerr << "RESULT: "; interval.print(std::cerr, mri_));
|
|
|
|
// Replace the interval with one of a NEW value number. Note that this
|
|
// value number isn't actually defined by an instruction, weird huh? :)
|
|
LiveRange LR(Start, End, interval.getNextValue(~0U, 0));
|
|
DEBUG(std::cerr << " replace range with " << LR);
|
|
interval.addRange(LR);
|
|
DEBUG(std::cerr << "RESULT: "; interval.print(std::cerr, mri_));
|
|
}
|
|
|
|
// In the case of PHI elimination, each variable definition is only
|
|
// live until the end of the block. We've already taken care of the
|
|
// rest of the live range.
|
|
unsigned defIndex = getDefIndex(MIIdx);
|
|
|
|
unsigned ValNum;
|
|
unsigned SrcReg, DstReg;
|
|
if (!tii_->isMoveInstr(*mi, SrcReg, DstReg))
|
|
ValNum = interval.getNextValue(~0U, 0);
|
|
else
|
|
ValNum = interval.getNextValue(defIndex, SrcReg);
|
|
|
|
LiveRange LR(defIndex,
|
|
getInstructionIndex(&mbb->back()) + InstrSlots::NUM, ValNum);
|
|
interval.addRange(LR);
|
|
DEBUG(std::cerr << " +" << LR);
|
|
}
|
|
}
|
|
|
|
DEBUG(std::cerr << '\n');
|
|
}
|
|
|
|
void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
|
|
MachineBasicBlock::iterator mi,
|
|
unsigned MIIdx,
|
|
LiveInterval &interval,
|
|
unsigned SrcReg) {
|
|
// A physical register cannot be live across basic block, so its
|
|
// lifetime must end somewhere in its defining basic block.
|
|
DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg));
|
|
typedef LiveVariables::killed_iterator KillIter;
|
|
|
|
unsigned baseIndex = MIIdx;
|
|
unsigned start = getDefIndex(baseIndex);
|
|
unsigned end = start;
|
|
|
|
// If it is not used after definition, it is considered dead at
|
|
// the instruction defining it. Hence its interval is:
|
|
// [defSlot(def), defSlot(def)+1)
|
|
if (lv_->RegisterDefIsDead(mi, interval.reg)) {
|
|
DEBUG(std::cerr << " dead");
|
|
end = getDefIndex(start) + 1;
|
|
goto exit;
|
|
}
|
|
|
|
// If it is not dead on definition, it must be killed by a
|
|
// subsequent instruction. Hence its interval is:
|
|
// [defSlot(def), useSlot(kill)+1)
|
|
while (++mi != MBB->end()) {
|
|
baseIndex += InstrSlots::NUM;
|
|
if (lv_->KillsRegister(mi, interval.reg)) {
|
|
DEBUG(std::cerr << " killed");
|
|
end = getUseIndex(baseIndex) + 1;
|
|
goto exit;
|
|
}
|
|
}
|
|
|
|
// The only case we should have a dead physreg here without a killing or
|
|
// instruction where we know it's dead is if it is live-in to the function
|
|
// and never used.
|
|
assert(!SrcReg && "physreg was not killed in defining block!");
|
|
end = getDefIndex(start) + 1; // It's dead.
|
|
|
|
exit:
|
|
assert(start < end && "did not find end of interval?");
|
|
|
|
LiveRange LR(start, end, interval.getNextValue(SrcReg != 0 ? start : ~0U,
|
|
SrcReg));
|
|
interval.addRange(LR);
|
|
DEBUG(std::cerr << " +" << LR << '\n');
|
|
}
|
|
|
|
void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
unsigned MIIdx,
|
|
unsigned reg) {
|
|
if (MRegisterInfo::isVirtualRegister(reg))
|
|
handleVirtualRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg));
|
|
else if (allocatableRegs_[reg]) {
|
|
unsigned SrcReg, DstReg;
|
|
if (!tii_->isMoveInstr(*MI, SrcReg, DstReg))
|
|
SrcReg = 0;
|
|
handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg), SrcReg);
|
|
for (const unsigned* AS = mri_->getAliasSet(reg); *AS; ++AS)
|
|
handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(*AS), 0);
|
|
}
|
|
}
|
|
|
|
/// computeIntervals - computes the live intervals for virtual
|
|
/// registers. for some ordering of the machine instructions [1,N] a
|
|
/// live interval is an interval [i, j) where 1 <= i <= j < N for
|
|
/// which a variable is live
|
|
void LiveIntervals::computeIntervals() {
|
|
DEBUG(std::cerr << "********** COMPUTING LIVE INTERVALS **********\n");
|
|
DEBUG(std::cerr << "********** Function: "
|
|
<< ((Value*)mf_->getFunction())->getName() << '\n');
|
|
bool IgnoreFirstInstr = mf_->livein_begin() != mf_->livein_end();
|
|
|
|
// Track the index of the current machine instr.
|
|
unsigned MIIndex = 0;
|
|
for (MachineFunction::iterator MBBI = mf_->begin(), E = mf_->end();
|
|
MBBI != E; ++MBBI) {
|
|
MachineBasicBlock *MBB = MBBI;
|
|
DEBUG(std::cerr << ((Value*)MBB->getBasicBlock())->getName() << ":\n");
|
|
|
|
MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
|
|
if (IgnoreFirstInstr) {
|
|
++MI;
|
|
IgnoreFirstInstr = false;
|
|
MIIndex += InstrSlots::NUM;
|
|
}
|
|
|
|
for (; MI != miEnd; ++MI) {
|
|
const TargetInstrDescriptor &TID = tii_->get(MI->getOpcode());
|
|
DEBUG(std::cerr << MIIndex << "\t" << *MI);
|
|
|
|
// Handle implicit defs.
|
|
if (TID.ImplicitDefs) {
|
|
for (const unsigned *ImpDef = TID.ImplicitDefs; *ImpDef; ++ImpDef)
|
|
handleRegisterDef(MBB, MI, MIIndex, *ImpDef);
|
|
}
|
|
|
|
// Handle explicit defs.
|
|
for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
// handle register defs - build intervals
|
|
if (MO.isRegister() && MO.getReg() && MO.isDef())
|
|
handleRegisterDef(MBB, MI, MIIndex, MO.getReg());
|
|
}
|
|
|
|
MIIndex += InstrSlots::NUM;
|
|
}
|
|
}
|
|
}
|
|
|
|
/// AdjustCopiesBackFrom - We found a non-trivially-coallescable copy with IntA
|
|
/// being the source and IntB being the dest, thus this defines a value number
|
|
/// in IntB. If the source value number (in IntA) is defined by a copy from B,
|
|
/// see if we can merge these two pieces of B into a single value number,
|
|
/// eliminating a copy. For example:
|
|
///
|
|
/// A3 = B0
|
|
/// ...
|
|
/// B1 = A3 <- this copy
|
|
///
|
|
/// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
|
|
/// value number to be replaced with B0 (which simplifies the B liveinterval).
|
|
///
|
|
/// This returns true if an interval was modified.
|
|
///
|
|
bool LiveIntervals::AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
|
|
MachineInstr *CopyMI) {
|
|
unsigned CopyIdx = getDefIndex(getInstructionIndex(CopyMI));
|
|
|
|
// BValNo is a value number in B that is defined by a copy from A. 'B3' in
|
|
// the example above.
|
|
LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
|
|
unsigned BValNo = BLR->ValId;
|
|
|
|
// Get the location that B is defined at. Two options: either this value has
|
|
// an unknown definition point or it is defined at CopyIdx. If unknown, we
|
|
// can't process it.
|
|
unsigned BValNoDefIdx = IntB.getInstForValNum(BValNo);
|
|
if (BValNoDefIdx == ~0U) return false;
|
|
assert(BValNoDefIdx == CopyIdx &&
|
|
"Copy doesn't define the value?");
|
|
|
|
// AValNo is the value number in A that defines the copy, A0 in the example.
|
|
LiveInterval::iterator AValLR = IntA.FindLiveRangeContaining(CopyIdx-1);
|
|
unsigned AValNo = AValLR->ValId;
|
|
|
|
// If AValNo is defined as a copy from IntB, we can potentially process this.
|
|
|
|
// Get the instruction that defines this value number.
|
|
unsigned SrcReg = IntA.getSrcRegForValNum(AValNo);
|
|
if (!SrcReg) return false; // Not defined by a copy.
|
|
|
|
// If the value number is not defined by a copy instruction, ignore it.
|
|
|
|
// If the source register comes from an interval other than IntB, we can't
|
|
// handle this.
|
|
if (rep(SrcReg) != IntB.reg) return false;
|
|
|
|
// Get the LiveRange in IntB that this value number starts with.
|
|
unsigned AValNoInstIdx = IntA.getInstForValNum(AValNo);
|
|
LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNoInstIdx-1);
|
|
|
|
// Make sure that the end of the live range is inside the same block as
|
|
// CopyMI.
|
|
MachineInstr *ValLREndInst = getInstructionFromIndex(ValLR->end-1);
|
|
if (!ValLREndInst ||
|
|
ValLREndInst->getParent() != CopyMI->getParent()) return false;
|
|
|
|
// Okay, we now know that ValLR ends in the same block that the CopyMI
|
|
// live-range starts. If there are no intervening live ranges between them in
|
|
// IntB, we can merge them.
|
|
if (ValLR+1 != BLR) return false;
|
|
|
|
DEBUG(std::cerr << "\nExtending: "; IntB.print(std::cerr, mri_));
|
|
|
|
// We are about to delete CopyMI, so need to remove it as the 'instruction
|
|
// that defines this value #'.
|
|
IntB.setValueNumberInfo(BValNo, std::make_pair(~0U, 0));
|
|
|
|
// Okay, we can merge them. We need to insert a new liverange:
|
|
// [ValLR.end, BLR.begin) of either value number, then we merge the
|
|
// two value numbers.
|
|
unsigned FillerStart = ValLR->end, FillerEnd = BLR->start;
|
|
IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
|
|
|
|
// If the IntB live range is assigned to a physical register, and if that
|
|
// physreg has aliases,
|
|
if (MRegisterInfo::isPhysicalRegister(IntB.reg)) {
|
|
for (const unsigned *AS = mri_->getAliasSet(IntB.reg); *AS; ++AS) {
|
|
LiveInterval &AliasLI = getInterval(*AS);
|
|
AliasLI.addRange(LiveRange(FillerStart, FillerEnd,
|
|
AliasLI.getNextValue(~0U, 0)));
|
|
}
|
|
}
|
|
|
|
// Okay, merge "B1" into the same value number as "B0".
|
|
if (BValNo != ValLR->ValId)
|
|
IntB.MergeValueNumberInto(BValNo, ValLR->ValId);
|
|
DEBUG(std::cerr << " result = "; IntB.print(std::cerr, mri_);
|
|
std::cerr << "\n");
|
|
|
|
// Finally, delete the copy instruction.
|
|
RemoveMachineInstrFromMaps(CopyMI);
|
|
CopyMI->eraseFromParent();
|
|
++numPeep;
|
|
return true;
|
|
}
|
|
|
|
|
|
/// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
|
|
/// which are the src/dst of the copy instruction CopyMI. This returns true
|
|
/// if the copy was successfully coallesced away, or if it is never possible
|
|
/// to coallesce these this copy, due to register constraints. It returns
|
|
/// false if it is not currently possible to coallesce this interval, but
|
|
/// it may be possible if other things get coallesced.
|
|
bool LiveIntervals::JoinCopy(MachineInstr *CopyMI,
|
|
unsigned SrcReg, unsigned DstReg) {
|
|
|
|
|
|
DEBUG(std::cerr << getInstructionIndex(CopyMI) << '\t' << *CopyMI);
|
|
|
|
// Get representative registers.
|
|
SrcReg = rep(SrcReg);
|
|
DstReg = rep(DstReg);
|
|
|
|
// If they are already joined we continue.
|
|
if (SrcReg == DstReg) {
|
|
DEBUG(std::cerr << "\tCopy already coallesced.\n");
|
|
return true; // Not coallescable.
|
|
}
|
|
|
|
// If they are both physical registers, we cannot join them.
|
|
if (MRegisterInfo::isPhysicalRegister(SrcReg) &&
|
|
MRegisterInfo::isPhysicalRegister(DstReg)) {
|
|
DEBUG(std::cerr << "\tCan not coallesce physregs.\n");
|
|
return true; // Not coallescable.
|
|
}
|
|
|
|
// We only join virtual registers with allocatable physical registers.
|
|
if (MRegisterInfo::isPhysicalRegister(SrcReg) && !allocatableRegs_[SrcReg]){
|
|
DEBUG(std::cerr << "\tSrc reg is unallocatable physreg.\n");
|
|
return true; // Not coallescable.
|
|
}
|
|
if (MRegisterInfo::isPhysicalRegister(DstReg) && !allocatableRegs_[DstReg]){
|
|
DEBUG(std::cerr << "\tDst reg is unallocatable physreg.\n");
|
|
return true; // Not coallescable.
|
|
}
|
|
|
|
// If they are not of the same register class, we cannot join them.
|
|
if (differingRegisterClasses(SrcReg, DstReg)) {
|
|
DEBUG(std::cerr << "\tSrc/Dest are different register classes.\n");
|
|
return true; // Not coallescable.
|
|
}
|
|
|
|
LiveInterval &SrcInt = getInterval(SrcReg);
|
|
LiveInterval &DestInt = getInterval(DstReg);
|
|
assert(SrcInt.reg == SrcReg && DestInt.reg == DstReg &&
|
|
"Register mapping is horribly broken!");
|
|
|
|
DEBUG(std::cerr << "\t\tInspecting "; SrcInt.print(std::cerr, mri_);
|
|
std::cerr << " and "; DestInt.print(std::cerr, mri_);
|
|
std::cerr << ": ");
|
|
|
|
// Okay, attempt to join these two intervals. On failure, this returns false.
|
|
// Otherwise, if one of the intervals being joined is a physreg, this method
|
|
// always canonicalizes DestInt to be it. The output "SrcInt" will not have
|
|
// been modified, so we can use this information below to update aliases.
|
|
if (!JoinIntervals(DestInt, SrcInt)) {
|
|
// Coallescing failed.
|
|
|
|
// If we can eliminate the copy without merging the live ranges, do so now.
|
|
if (AdjustCopiesBackFrom(SrcInt, DestInt, CopyMI))
|
|
return true;
|
|
|
|
// Otherwise, we are unable to join the intervals.
|
|
DEBUG(std::cerr << "Interference!\n");
|
|
return false;
|
|
}
|
|
|
|
bool Swapped = SrcReg == DestInt.reg;
|
|
if (Swapped)
|
|
std::swap(SrcReg, DstReg);
|
|
assert(MRegisterInfo::isVirtualRegister(SrcReg) &&
|
|
"LiveInterval::join didn't work right!");
|
|
|
|
// If we're about to merge live ranges into a physical register live range,
|
|
// we have to update any aliased register's live ranges to indicate that they
|
|
// have clobbered values for this range.
|
|
if (MRegisterInfo::isPhysicalRegister(DstReg)) {
|
|
for (const unsigned *AS = mri_->getAliasSet(DstReg); *AS; ++AS)
|
|
getInterval(*AS).MergeInClobberRanges(SrcInt);
|
|
}
|
|
|
|
DEBUG(std::cerr << "\n\t\tJoined. Result = "; DestInt.print(std::cerr, mri_);
|
|
std::cerr << "\n");
|
|
|
|
// If the intervals were swapped by Join, swap them back so that the register
|
|
// mapping (in the r2i map) is correct.
|
|
if (Swapped) SrcInt.swap(DestInt);
|
|
r2iMap_.erase(SrcReg);
|
|
r2rMap_[SrcReg] = DstReg;
|
|
|
|
// Finally, delete the copy instruction.
|
|
RemoveMachineInstrFromMaps(CopyMI);
|
|
CopyMI->eraseFromParent();
|
|
++numPeep;
|
|
++numJoins;
|
|
return true;
|
|
}
|
|
|
|
/// ComputeUltimateVN - Assuming we are going to join two live intervals,
|
|
/// compute what the resultant value numbers for each value in the input two
|
|
/// ranges will be. This is complicated by copies between the two which can
|
|
/// and will commonly cause multiple value numbers to be merged into one.
|
|
///
|
|
/// VN is the value number that we're trying to resolve. InstDefiningValue
|
|
/// keeps track of the new InstDefiningValue assignment for the result
|
|
/// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
|
|
/// whether a value in this or other is a copy from the opposite set.
|
|
/// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
|
|
/// already been assigned.
|
|
///
|
|
/// ThisFromOther[x] - If x is defined as a copy from the other interval, this
|
|
/// contains the value number the copy is from.
|
|
///
|
|
static unsigned ComputeUltimateVN(unsigned VN,
|
|
SmallVector<std::pair<unsigned,
|
|
unsigned>, 16> &ValueNumberInfo,
|
|
SmallVector<int, 16> &ThisFromOther,
|
|
SmallVector<int, 16> &OtherFromThis,
|
|
SmallVector<int, 16> &ThisValNoAssignments,
|
|
SmallVector<int, 16> &OtherValNoAssignments,
|
|
LiveInterval &ThisLI, LiveInterval &OtherLI) {
|
|
// If the VN has already been computed, just return it.
|
|
if (ThisValNoAssignments[VN] >= 0)
|
|
return ThisValNoAssignments[VN];
|
|
// assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?");
|
|
|
|
// If this val is not a copy from the other val, then it must be a new value
|
|
// number in the destination.
|
|
int OtherValNo = ThisFromOther[VN];
|
|
if (OtherValNo == -1) {
|
|
ValueNumberInfo.push_back(ThisLI.getValNumInfo(VN));
|
|
return ThisValNoAssignments[VN] = ValueNumberInfo.size()-1;
|
|
}
|
|
|
|
// Otherwise, this *is* a copy from the RHS. If the other side has already
|
|
// been computed, return it.
|
|
if (OtherValNoAssignments[OtherValNo] >= 0)
|
|
return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo];
|
|
|
|
// Mark this value number as currently being computed, then ask what the
|
|
// ultimate value # of the other value is.
|
|
ThisValNoAssignments[VN] = -2;
|
|
unsigned UltimateVN =
|
|
ComputeUltimateVN(OtherValNo, ValueNumberInfo,
|
|
OtherFromThis, ThisFromOther,
|
|
OtherValNoAssignments, ThisValNoAssignments,
|
|
OtherLI, ThisLI);
|
|
return ThisValNoAssignments[VN] = UltimateVN;
|
|
}
|
|
|
|
static bool InVector(unsigned Val, const SmallVector<unsigned, 8> &V) {
|
|
return std::find(V.begin(), V.end(), Val) != V.end();
|
|
}
|
|
|
|
/// SimpleJoin - Attempt to joint the specified interval into this one. The
|
|
/// caller of this method must guarantee that the RHS only contains a single
|
|
/// value number and that the RHS is not defined by a copy from this
|
|
/// interval. This returns false if the intervals are not joinable, or it
|
|
/// joins them and returns true.
|
|
bool LiveIntervals::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS) {
|
|
assert(RHS.containsOneValue());
|
|
|
|
// Some number (potentially more than one) value numbers in the current
|
|
// interval may be defined as copies from the RHS. Scan the overlapping
|
|
// portions of the LHS and RHS, keeping track of this and looking for
|
|
// overlapping live ranges that are NOT defined as copies. If these exist, we
|
|
// cannot coallesce.
|
|
|
|
LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
|
|
LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
|
|
|
|
if (LHSIt->start < RHSIt->start) {
|
|
LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
|
|
if (LHSIt != LHS.begin()) --LHSIt;
|
|
} else if (RHSIt->start < LHSIt->start) {
|
|
RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
|
|
if (RHSIt != RHS.begin()) --RHSIt;
|
|
}
|
|
|
|
SmallVector<unsigned, 8> EliminatedLHSVals;
|
|
|
|
while (1) {
|
|
// Determine if these live intervals overlap.
|
|
bool Overlaps = false;
|
|
if (LHSIt->start <= RHSIt->start)
|
|
Overlaps = LHSIt->end > RHSIt->start;
|
|
else
|
|
Overlaps = RHSIt->end > LHSIt->start;
|
|
|
|
// If the live intervals overlap, there are two interesting cases: if the
|
|
// LHS interval is defined by a copy from the RHS, it's ok and we record
|
|
// that the LHS value # is the same as the RHS. If it's not, then we cannot
|
|
// coallesce these live ranges and we bail out.
|
|
if (Overlaps) {
|
|
// If we haven't already recorded that this value # is safe, check it.
|
|
if (!InVector(LHSIt->ValId, EliminatedLHSVals)) {
|
|
// Copy from the RHS?
|
|
unsigned SrcReg = LHS.getSrcRegForValNum(LHSIt->ValId);
|
|
if (rep(SrcReg) != RHS.reg)
|
|
return false; // Nope, bail out.
|
|
|
|
EliminatedLHSVals.push_back(LHSIt->ValId);
|
|
}
|
|
|
|
// We know this entire LHS live range is okay, so skip it now.
|
|
if (++LHSIt == LHSEnd) break;
|
|
continue;
|
|
}
|
|
|
|
if (LHSIt->end < RHSIt->end) {
|
|
if (++LHSIt == LHSEnd) break;
|
|
} else {
|
|
// One interesting case to check here. It's possible that we have
|
|
// something like "X3 = Y" which defines a new value number in the LHS,
|
|
// and is the last use of this liverange of the RHS. In this case, we
|
|
// want to notice this copy (so that it gets coallesced away) even though
|
|
// the live ranges don't actually overlap.
|
|
if (LHSIt->start == RHSIt->end) {
|
|
if (InVector(LHSIt->ValId, EliminatedLHSVals)) {
|
|
// We already know that this value number is going to be merged in
|
|
// if coallescing succeeds. Just skip the liverange.
|
|
if (++LHSIt == LHSEnd) break;
|
|
} else {
|
|
// Otherwise, if this is a copy from the RHS, mark it as being merged
|
|
// in.
|
|
if (rep(LHS.getSrcRegForValNum(LHSIt->ValId)) == RHS.reg) {
|
|
EliminatedLHSVals.push_back(LHSIt->ValId);
|
|
|
|
// We know this entire LHS live range is okay, so skip it now.
|
|
if (++LHSIt == LHSEnd) break;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (++RHSIt == RHSEnd) break;
|
|
}
|
|
}
|
|
|
|
// If we got here, we know that the coallescing will be successful and that
|
|
// the value numbers in EliminatedLHSVals will all be merged together. Since
|
|
// the most common case is that EliminatedLHSVals has a single number, we
|
|
// optimize for it: if there is more than one value, we merge them all into
|
|
// the lowest numbered one, then handle the interval as if we were merging
|
|
// with one value number.
|
|
unsigned LHSValNo;
|
|
if (EliminatedLHSVals.size() > 1) {
|
|
// Loop through all the equal value numbers merging them into the smallest
|
|
// one.
|
|
unsigned Smallest = EliminatedLHSVals[0];
|
|
for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) {
|
|
if (EliminatedLHSVals[i] < Smallest) {
|
|
// Merge the current notion of the smallest into the smaller one.
|
|
LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]);
|
|
Smallest = EliminatedLHSVals[i];
|
|
} else {
|
|
// Merge into the smallest.
|
|
LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest);
|
|
}
|
|
}
|
|
LHSValNo = Smallest;
|
|
} else {
|
|
assert(!EliminatedLHSVals.empty() && "No copies from the RHS?");
|
|
LHSValNo = EliminatedLHSVals[0];
|
|
}
|
|
|
|
// Okay, now that there is a single LHS value number that we're merging the
|
|
// RHS into, update the value number info for the LHS to indicate that the
|
|
// value number is defined where the RHS value number was.
|
|
LHS.setValueNumberInfo(LHSValNo, RHS.getValNumInfo(0));
|
|
|
|
// Okay, the final step is to loop over the RHS live intervals, adding them to
|
|
// the LHS.
|
|
LHS.MergeRangesInAsValue(RHS, LHSValNo);
|
|
LHS.weight += RHS.weight;
|
|
|
|
return true;
|
|
}
|
|
|
|
/// JoinIntervals - Attempt to join these two intervals. On failure, this
|
|
/// returns false. Otherwise, if one of the intervals being joined is a
|
|
/// physreg, this method always canonicalizes LHS to be it. The output
|
|
/// "RHS" will not have been modified, so we can use this information
|
|
/// below to update aliases.
|
|
bool LiveIntervals::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS) {
|
|
// Compute the final value assignment, assuming that the live ranges can be
|
|
// coallesced.
|
|
SmallVector<int, 16> LHSValNoAssignments;
|
|
SmallVector<int, 16> RHSValNoAssignments;
|
|
SmallVector<std::pair<unsigned,unsigned>, 16> ValueNumberInfo;
|
|
|
|
// Compute ultimate value numbers for the LHS and RHS values.
|
|
if (RHS.containsOneValue()) {
|
|
// Copies from a liveinterval with a single value are simple to handle and
|
|
// very common, handle the special case here. This is important, because
|
|
// often RHS is small and LHS is large (e.g. a physreg).
|
|
|
|
// Find out if the RHS is defined as a copy from some value in the LHS.
|
|
int RHSValID = -1;
|
|
std::pair<unsigned,unsigned> RHSValNoInfo;
|
|
unsigned RHSSrcReg = RHS.getSrcRegForValNum(0);
|
|
if ((RHSSrcReg == 0 || rep(RHSSrcReg) != LHS.reg)) {
|
|
// If RHS is not defined as a copy from the LHS, we can use simpler and
|
|
// faster checks to see if the live ranges are coallescable. This joiner
|
|
// can't swap the LHS/RHS intervals though.
|
|
if (!MRegisterInfo::isPhysicalRegister(RHS.reg)) {
|
|
return SimpleJoin(LHS, RHS);
|
|
} else {
|
|
RHSValNoInfo = RHS.getValNumInfo(0);
|
|
}
|
|
} else {
|
|
// It was defined as a copy from the LHS, find out what value # it is.
|
|
unsigned ValInst = RHS.getInstForValNum(0);
|
|
RHSValID = LHS.getLiveRangeContaining(ValInst-1)->ValId;
|
|
RHSValNoInfo = LHS.getValNumInfo(RHSValID);
|
|
}
|
|
|
|
LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
|
|
RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
|
|
ValueNumberInfo.resize(LHS.getNumValNums());
|
|
|
|
// Okay, *all* of the values in LHS that are defined as a copy from RHS
|
|
// should now get updated.
|
|
for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) {
|
|
if (unsigned LHSSrcReg = LHS.getSrcRegForValNum(VN)) {
|
|
if (rep(LHSSrcReg) != RHS.reg) {
|
|
// If this is not a copy from the RHS, its value number will be
|
|
// unmodified by the coallescing.
|
|
ValueNumberInfo[VN] = LHS.getValNumInfo(VN);
|
|
LHSValNoAssignments[VN] = VN;
|
|
} else if (RHSValID == -1) {
|
|
// Otherwise, it is a copy from the RHS, and we don't already have a
|
|
// value# for it. Keep the current value number, but remember it.
|
|
LHSValNoAssignments[VN] = RHSValID = VN;
|
|
ValueNumberInfo[VN] = RHSValNoInfo;
|
|
} else {
|
|
// Otherwise, use the specified value #.
|
|
LHSValNoAssignments[VN] = RHSValID;
|
|
if (VN != (unsigned)RHSValID)
|
|
ValueNumberInfo[VN].first = ~1U;
|
|
else
|
|
ValueNumberInfo[VN] = RHSValNoInfo;
|
|
}
|
|
} else {
|
|
ValueNumberInfo[VN] = LHS.getValNumInfo(VN);
|
|
LHSValNoAssignments[VN] = VN;
|
|
}
|
|
}
|
|
|
|
assert(RHSValID != -1 && "Didn't find value #?");
|
|
RHSValNoAssignments[0] = RHSValID;
|
|
|
|
} else {
|
|
// Loop over the value numbers of the LHS, seeing if any are defined from
|
|
// the RHS.
|
|
SmallVector<int, 16> LHSValsDefinedFromRHS;
|
|
LHSValsDefinedFromRHS.resize(LHS.getNumValNums(), -1);
|
|
for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) {
|
|
unsigned ValSrcReg = LHS.getSrcRegForValNum(VN);
|
|
if (ValSrcReg == 0) // Src not defined by a copy?
|
|
continue;
|
|
|
|
// DstReg is known to be a register in the LHS interval. If the src is
|
|
// from the RHS interval, we can use its value #.
|
|
if (rep(ValSrcReg) != RHS.reg)
|
|
continue;
|
|
|
|
// Figure out the value # from the RHS.
|
|
unsigned ValInst = LHS.getInstForValNum(VN);
|
|
LHSValsDefinedFromRHS[VN] = RHS.getLiveRangeContaining(ValInst-1)->ValId;
|
|
}
|
|
|
|
// Loop over the value numbers of the RHS, seeing if any are defined from
|
|
// the LHS.
|
|
SmallVector<int, 16> RHSValsDefinedFromLHS;
|
|
RHSValsDefinedFromLHS.resize(RHS.getNumValNums(), -1);
|
|
for (unsigned VN = 0, e = RHS.getNumValNums(); VN != e; ++VN) {
|
|
unsigned ValSrcReg = RHS.getSrcRegForValNum(VN);
|
|
if (ValSrcReg == 0) // Src not defined by a copy?
|
|
continue;
|
|
|
|
// DstReg is known to be a register in the RHS interval. If the src is
|
|
// from the LHS interval, we can use its value #.
|
|
if (rep(ValSrcReg) != LHS.reg)
|
|
continue;
|
|
|
|
// Figure out the value # from the LHS.
|
|
unsigned ValInst = RHS.getInstForValNum(VN);
|
|
RHSValsDefinedFromLHS[VN] = LHS.getLiveRangeContaining(ValInst-1)->ValId;
|
|
}
|
|
|
|
LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
|
|
RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
|
|
ValueNumberInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
|
|
|
|
for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) {
|
|
if (LHSValNoAssignments[VN] >= 0 || LHS.getInstForValNum(VN) == ~2U)
|
|
continue;
|
|
ComputeUltimateVN(VN, ValueNumberInfo,
|
|
LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
|
|
LHSValNoAssignments, RHSValNoAssignments, LHS, RHS);
|
|
}
|
|
for (unsigned VN = 0, e = RHS.getNumValNums(); VN != e; ++VN) {
|
|
if (RHSValNoAssignments[VN] >= 0 || RHS.getInstForValNum(VN) == ~2U)
|
|
continue;
|
|
// If this value number isn't a copy from the LHS, it's a new number.
|
|
if (RHSValsDefinedFromLHS[VN] == -1) {
|
|
ValueNumberInfo.push_back(RHS.getValNumInfo(VN));
|
|
RHSValNoAssignments[VN] = ValueNumberInfo.size()-1;
|
|
continue;
|
|
}
|
|
|
|
ComputeUltimateVN(VN, ValueNumberInfo,
|
|
RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
|
|
RHSValNoAssignments, LHSValNoAssignments, RHS, LHS);
|
|
}
|
|
}
|
|
|
|
// Armed with the mappings of LHS/RHS values to ultimate values, walk the
|
|
// interval lists to see if these intervals are coallescable.
|
|
LiveInterval::const_iterator I = LHS.begin();
|
|
LiveInterval::const_iterator IE = LHS.end();
|
|
LiveInterval::const_iterator J = RHS.begin();
|
|
LiveInterval::const_iterator JE = RHS.end();
|
|
|
|
// Skip ahead until the first place of potential sharing.
|
|
if (I->start < J->start) {
|
|
I = std::upper_bound(I, IE, J->start);
|
|
if (I != LHS.begin()) --I;
|
|
} else if (J->start < I->start) {
|
|
J = std::upper_bound(J, JE, I->start);
|
|
if (J != RHS.begin()) --J;
|
|
}
|
|
|
|
while (1) {
|
|
// Determine if these two live ranges overlap.
|
|
bool Overlaps;
|
|
if (I->start < J->start) {
|
|
Overlaps = I->end > J->start;
|
|
} else {
|
|
Overlaps = J->end > I->start;
|
|
}
|
|
|
|
// If so, check value # info to determine if they are really different.
|
|
if (Overlaps) {
|
|
// If the live range overlap will map to the same value number in the
|
|
// result liverange, we can still coallesce them. If not, we can't.
|
|
if (LHSValNoAssignments[I->ValId] != RHSValNoAssignments[J->ValId])
|
|
return false;
|
|
}
|
|
|
|
if (I->end < J->end) {
|
|
++I;
|
|
if (I == IE) break;
|
|
} else {
|
|
++J;
|
|
if (J == JE) break;
|
|
}
|
|
}
|
|
|
|
// If we get here, we know that we can coallesce the live ranges. Ask the
|
|
// intervals to coallesce themselves now.
|
|
LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0],
|
|
ValueNumberInfo);
|
|
return true;
|
|
}
|
|
|
|
|
|
namespace {
|
|
// DepthMBBCompare - Comparison predicate that sort first based on the loop
|
|
// depth of the basic block (the unsigned), and then on the MBB number.
|
|
struct DepthMBBCompare {
|
|
typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
|
|
bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
|
|
if (LHS.first > RHS.first) return true; // Deeper loops first
|
|
return LHS.first == RHS.first &&
|
|
LHS.second->getNumber() < RHS.second->getNumber();
|
|
}
|
|
};
|
|
}
|
|
|
|
|
|
void LiveIntervals::CopyCoallesceInMBB(MachineBasicBlock *MBB,
|
|
std::vector<CopyRec> &TryAgain) {
|
|
DEBUG(std::cerr << ((Value*)MBB->getBasicBlock())->getName() << ":\n");
|
|
|
|
for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
|
|
MII != E;) {
|
|
MachineInstr *Inst = MII++;
|
|
|
|
// If this isn't a copy, we can't join intervals.
|
|
unsigned SrcReg, DstReg;
|
|
if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg)) continue;
|
|
|
|
if (!JoinCopy(Inst, SrcReg, DstReg))
|
|
TryAgain.push_back(getCopyRec(Inst, SrcReg, DstReg));
|
|
}
|
|
}
|
|
|
|
|
|
void LiveIntervals::joinIntervals() {
|
|
DEBUG(std::cerr << "********** JOINING INTERVALS ***********\n");
|
|
|
|
std::vector<CopyRec> TryAgainList;
|
|
|
|
const LoopInfo &LI = getAnalysis<LoopInfo>();
|
|
if (LI.begin() == LI.end()) {
|
|
// If there are no loops in the function, join intervals in function order.
|
|
for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
|
|
I != E; ++I)
|
|
CopyCoallesceInMBB(I, TryAgainList);
|
|
} else {
|
|
// Otherwise, join intervals in inner loops before other intervals.
|
|
// Unfortunately we can't just iterate over loop hierarchy here because
|
|
// there may be more MBB's than BB's. Collect MBB's for sorting.
|
|
std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
|
|
for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
|
|
I != E; ++I)
|
|
MBBs.push_back(std::make_pair(LI.getLoopDepth(I->getBasicBlock()), I));
|
|
|
|
// Sort by loop depth.
|
|
std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
|
|
|
|
// Finally, join intervals in loop nest order.
|
|
for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
|
|
CopyCoallesceInMBB(MBBs[i].second, TryAgainList);
|
|
}
|
|
|
|
// Joining intervals can allow other intervals to be joined. Iteratively join
|
|
// until we make no progress.
|
|
bool ProgressMade = true;
|
|
while (ProgressMade) {
|
|
ProgressMade = false;
|
|
|
|
for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
|
|
CopyRec &TheCopy = TryAgainList[i];
|
|
if (TheCopy.MI &&
|
|
JoinCopy(TheCopy.MI, TheCopy.SrcReg, TheCopy.DstReg)) {
|
|
TheCopy.MI = 0; // Mark this one as done.
|
|
ProgressMade = true;
|
|
}
|
|
}
|
|
}
|
|
|
|
DEBUG(std::cerr << "*** Register mapping ***\n");
|
|
DEBUG(for (int i = 0, e = r2rMap_.size(); i != e; ++i)
|
|
if (r2rMap_[i]) {
|
|
std::cerr << " reg " << i << " -> ";
|
|
printRegName(r2rMap_[i]);
|
|
std::cerr << "\n";
|
|
});
|
|
}
|
|
|
|
/// Return true if the two specified registers belong to different register
|
|
/// classes. The registers may be either phys or virt regs.
|
|
bool LiveIntervals::differingRegisterClasses(unsigned RegA,
|
|
unsigned RegB) const {
|
|
|
|
// Get the register classes for the first reg.
|
|
if (MRegisterInfo::isPhysicalRegister(RegA)) {
|
|
assert(MRegisterInfo::isVirtualRegister(RegB) &&
|
|
"Shouldn't consider two physregs!");
|
|
return !mf_->getSSARegMap()->getRegClass(RegB)->contains(RegA);
|
|
}
|
|
|
|
// Compare against the regclass for the second reg.
|
|
const TargetRegisterClass *RegClass = mf_->getSSARegMap()->getRegClass(RegA);
|
|
if (MRegisterInfo::isVirtualRegister(RegB))
|
|
return RegClass != mf_->getSSARegMap()->getRegClass(RegB);
|
|
else
|
|
return !RegClass->contains(RegB);
|
|
}
|
|
|
|
LiveInterval LiveIntervals::createInterval(unsigned reg) {
|
|
float Weight = MRegisterInfo::isPhysicalRegister(reg) ?
|
|
(float)HUGE_VAL : 0.0F;
|
|
return LiveInterval(reg, Weight);
|
|
}
|