Juergen Ributzka faf93a6e0c [FastIsel][AArch64] Fix a think-o in address computation. ... When looking through sign/zero-extensions the code would always assume there is such an extension instruction and use the wrong operand for the address. There was also a minor issue in the handling of 'AND' instructions. I accidentially used a 'cast' instead of a 'dyn_cast'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218161 91177308-0d34-0410-b5e6-96231b3b80d8		2014-09-19 22:23:46 +00:00
..
AArch64	[FastIsel][AArch64] Fix a think-o in address computation.	2014-09-19 22:23:46 +00:00
ARM	[ARM] Do not perform a tail call when the caller returns several values.	2014-09-18 21:17:50 +00:00
CPP
Generic	Add a regression test to sanity check the PBQP allocator.	2014-09-03 18:04:10 +00:00
Hexagon	DebugInfo: Assert that any CU for which debug_loc lists are emitted, has at least one range.	2014-08-06 00:21:25 +00:00
Inputs
Mips	Add mips32 r1 to the list of supported targets for Mips fast-isel	2014-09-15 20:30:25 +00:00
MSP430	Drop the W postfix on the 16-bit registers.	2014-09-10 06:58:14 +00:00
NVPTX	[MachineSink] Use the real post dominator tree	2014-09-01 03:47:25 +00:00
PowerPC	Optionally enable more-aggressive FMA formation in DAGCombine	2014-09-19 11:42:56 +00:00
R600	R600/SI: Fix test to prepare for scheduler	2014-09-19 18:11:16 +00:00
SPARC	Add back tests for empty function in SPARC and PowerPC.	2014-09-15 22:11:07 +00:00
SystemZ
Thumb	Check-label a bit more specific	2014-09-03 13:32:08 +00:00
Thumb2	ARM / x86_64 varargs: Don't save regparms in prologue without va_start	2014-08-22 21:59:26 +00:00
X86	[x86] Fully generalize the zext lowering in the new vector shuffle	2014-09-19 20:00:32 +00:00
XCore