Tim Northover 630c5e06d6 AArch64: use RegisterOperand for NEON registers. ... Previously we modelled VPR128 and VPR64 as essentially identical register-classes containing V0-V31 (which had Q0-Q31 as "sub_alias" sub-registers). This model is starting to cause significant problems for code generation, particularly writing EXTRACT/INSERT_SUBREG patterns for converting between the two. The change here switches to classifying VPR64 & VPR128 as RegisterOperands, which are essentially aliases for RegisterClasses with different parsing and printing behaviour. This fits almost exactly with their real status (VPR128 == FPR128 printed strangely, VPR64 == FPR64 printed strangely). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190665 91177308-0d34-0410-b5e6-96231b3b80d8		2013-09-13 07:26:52 +00:00
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a64-ignored-fields.txt	AArch64: remove post-encoder method from FCMP (immediate) instructions.	2013-02-28 14:46:14 +00:00
basic-a64-instructions.txt	Add AArch64 CRC32 instructions	2013-02-06 09:13:13 +00:00
basic-a64-undefined.txt
basic-a64-unpredictable.txt
gicv3-regs.txt	AArch64: implement GICv3 system registers	2013-03-28 14:30:46 +00:00
ldp-offset-predictable.txt
ldp-postind.predictable.txt
ldp-preind.predictable.txt
lit.local.cfg	[tests] Cleanup initialization of test suffixes.	2013-08-16 00:37:11 +00:00
neon-instructions.txt	AArch64: use RegisterOperand for NEON registers.	2013-09-13 07:26:52 +00:00
trace-regs.txt	AArch64: implement ETMv4 trace system registers.	2013-04-03 12:31:29 +00:00