James Molloy fca7f5c585 [ARM64-BE] Implement the lane-twiddling logic at AAPCS boundaries for big endian. ... The AAPCS states that values passed in registers must have a value as though they had been loaded with "LDR". LDR is equivalent to "LD1.64 vX.1D" - that is, loading scalars to vector registers and loading 1-element vectors is equivalent. The logic implemented here is to ensure that at all call boundaries and during formal argument lowering all vectors are treated as their bitwidth-based floating point scalar counterpart, which is always one of f64 or f128 (v2i32 -> f64, v4i32 -> f128 etc). A BITCAST is inserted so that the appropriate REV will be generated during code generation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208198 91177308-0d34-0410-b5e6-96231b3b80d8		2014-05-07 12:33:41 +00:00
..
Analysis	[C++11] Add NArySCEV->Operands iterator range	2014-05-07 06:07:47 +00:00
AsmParser
Bitcode	[IR] Make {extract,insert}element accept an index of any integer type.	2014-05-01 22:12:39 +00:00
CodeGen	[BUG][REFACTOR]	2014-05-07 09:51:22 +00:00
DebugInfo	[DWARF parser] Cleanup code in DWARFDebugLine.	2014-04-30 00:09:19 +00:00
ExecutionEngine	[ARM64] Try and make the ELF MCJIT *slightly* less broken for ARM64.	2014-04-30 10:15:41 +00:00
IR	[BUG][REFACTOR]	2014-05-07 09:51:22 +00:00
IRReader
LineEditor
Linker	Be more strict about not calling setAlignment on global aliases.	2014-05-06 14:51:36 +00:00
LTO	Use a range loop.	2014-05-05 20:06:41 +00:00
MC	Allow using normal .eh_frame based unwinding on ARM. Use the same	2014-05-07 07:49:34 +00:00
Object	[ELFYAML] Group ELF header falgs to target specific blocks. Handle flags	2014-05-03 11:39:50 +00:00
Option
ProfileData	Fixing a cast-qual warning. getBufferStart() and getBufferEnd() both return a const char *, so casting to non-const was triggering a warning (even though the assignment and usage was always const anyway).	2014-05-01 17:16:24 +00:00
Support	[Support/MemoryBuffer] Remove the assertion that the file size did not shrink.	2014-05-06 23:30:56 +00:00
TableGen	[tablegen] Add !listconcat operator with the similar semantics as !strconcat	2014-05-07 10:13:19 +00:00
Target	[ARM64-BE] Implement the lane-twiddling logic at AAPCS boundaries for big endian.	2014-05-07 12:33:41 +00:00
Transforms	MergeFunctions Pass, introduced total ordering among values.	2014-05-07 11:11:39 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile