Sasa Stankovic fce699d88a [mips] Expand BuildPairF64 to a spill and reload when the O32 FPXX ABI is ... enabled and mthc1 and dmtc1 are not available (e.g. on MIPS32r1) This prevents the upper 32-bits of a double precision value from being moved to the FPU with mtc1 to an odd-numbered FPU register. This is necessary to ensure that the code generated executes correctly regardless of the current FPU mode. MIPS32r2 and above continues to use mtc1/mthc1, while MIPS-IV and above continue to use dmtc1. Differential Revision: http://reviews.llvm.org/D4465 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212930 91177308-0d34-0410-b5e6-96231b3b80d8		2014-07-14 09:40:29 +00:00
..
AArch64	AArch64: add support for llvm.aarch64.hint intrinsic	2014-07-12 21:20:49 +00:00
ARM	Support lowering of empty aggregates.	2014-07-14 06:22:36 +00:00
CPP
Generic
Hexagon
Inputs
Mips	[mips] Expand BuildPairF64 to a spill and reload when the O32 FPXX ABI is	2014-07-14 09:40:29 +00:00
MSP430
NVPTX	[NVPTX] Add reflect intrinsic (better than matching by function name)	2014-06-27 18:36:11 +00:00
PowerPC	[PowerPC] Fix invalid displacement created by LocalStackAlloc	2014-07-11 17:19:31 +00:00
R600	R600: Run more tests with promote alloca disabled.	2014-07-13 02:46:17 +00:00
SPARC
SystemZ
Thumb
Thumb2	ARM: Fix TPsoft for Thumb mode	2014-06-24 15:45:59 +00:00
X86	[DAGCombiner] Fix a crash caused by a missing check for legal type when trying to fold shuffles.	2014-07-13 21:02:14 +00:00
XCore	llvm/test/CodeGen/XCore/dwarf_debug.ll: Fix not to be affected by *-win32.	2014-07-04 11:58:03 +00:00