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14e97c4f51
Summary: To make this work for both AFGR64 and FGR64 register sets, I've had to make the instruction definition consistent with the white lie (that it reads the lower 32-bits of the register) when they are generated by expandBuildPairF64(). Corrected the definition of hasMips32r2() and hasMips64r2() to include MIPS32r6 and MIPS64r6. Depends on D3956 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3957 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210771 91177308-0d34-0410-b5e6-96231b3b80d8
39 lines
1.3 KiB
LLVM
39 lines
1.3 KiB
LLVM
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
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; RUN: < %s | FileCheck %s
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@f = common global float 0.000000e+00, align 4
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@de = common global double 0.000000e+00, align 8
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; Function Attrs: nounwind
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define void @f1() #0 {
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entry:
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store float 0x3FFA76C8C0000000, float* @f, align 4
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ret void
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; CHECK: .ent f1
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; CHECK: lui $[[REG1:[0-9]+]], 16339
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; CHECK: ori $[[REG2:[0-9]+]], $[[REG1]], 46662
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; CHECK: mtc1 $[[REG2]], $f[[REG3:[0-9]+]]
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; CHECK: lw $[[REG4:[0-9]+]], %got(f)(${{[0-9]+}})
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; CHECK: swc1 $f[[REG3]], 0($[[REG4]])
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; CHECK: .end f1
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}
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; Function Attrs: nounwind
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define void @d1() #0 {
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entry:
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store double 1.234567e+00, double* @de, align 8
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; CHECK: .ent d1
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; CHECK: lui $[[REG1a:[0-9]+]], 16371
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; CHECK: ori $[[REG2a:[0-9]+]], $[[REG1a]], 49353
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; CHECK: lui $[[REG1b:[0-9]+]], 21403
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; CHECK: ori $[[REG2b:[0-9]+]], $[[REG1b]], 34951
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; CHECK: mtc1 $[[REG2b]], $f[[REG3:[0-9]+]]
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; CHECK: mthc1 $[[REG2a]], $f[[REG3]]
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; CHECK: sdc1 $f[[REG3]], 0(${{[0-9]+}})
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; CHECK: .end d1
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ret void
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}
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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