Bruno Cardoso Lopes 8e03a821f9 Not sure how CMPPS and CMPPD had already ever worked, I guess it didn't. ... However with this fix it does now. Basically the operand order for the x86 target specific node is not the same as the instruction, but since the intrinsic need that specific order at the instruction definition, just change the order during legalization. Also, there were some wrong invertions of condition codes, such as GE => LE, GT => LT, fix that too. Fix PR10907. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139528 91177308-0d34-0410-b5e6-96231b3b80d8		2011-09-12 19:30:40 +00:00
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Alpha
ARM	Fix mistake in test runline.	2011-09-12 17:32:58 +00:00
Blackfin
CBackend	Revert r137134. It breaks some code as Eli pointed out.	2011-08-09 18:56:35 +00:00
CellSPU	Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction.	2011-09-02 10:05:01 +00:00
CPP
Generic	This test is already covered by llvm/trunk/test/CodeGen/X86/vsel.ll	2011-09-08 08:43:23 +00:00
MBlaze
Mips	Fix test cases.	2011-09-09 23:14:58 +00:00
MSP430
PowerPC	Split the init.trampoline intrinsic, which currently combines GCC's	2011-09-06 13:37:06 +00:00
PTX	PTX: Add initial support for device function calls	2011-08-09 17:36:31 +00:00
SPARC
SystemZ
Thumb	Disable these tests harder. They're XFAIL'd, but that means they still run, and	2011-09-06 22:08:18 +00:00
Thumb2	Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical	2011-08-30 01:34:54 +00:00
X86	Not sure how CMPPS and CMPPD had already ever worked, I guess it didn't.	2011-09-12 19:30:40 +00:00
XCore	Associate a MemOperand with LDWCP nodes introduced during ISel.	2011-09-12 14:43:23 +00:00