Tim Northover fef8e383eb ARM64: use 32-bit moves for constants where possible. ... If we know that a particular 64-bit constant has all high bits zero, then we can rely on the fact that 32-bit ARM64 instructions automatically zero out the high bits of an x-register. This gives the expansion logic less constraints to satisfy and so sometimes allows it to pick better sequences. Came up while porting test/CodeGen/AArch64/movw-consts.ll: this will allow a 32-bit MOVN to be used in @test8 soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206379 91177308-0d34-0410-b5e6-96231b3b80d8		2014-04-16 11:52:51 +00:00
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Analysis	Fix a bug in which BranchProbabilityInfo wasn't setting branch weights of basic blocks inside loops correctly.	2014-04-14 16:56:19 +00:00
Assembler
Bindings
Bitcode	AsmParser: add a warning for compatibility parsing	2014-04-05 22:42:53 +00:00
BugPoint
CodeGen	ARM64: use 32-bit moves for constants where possible.	2014-04-16 11:52:51 +00:00
DebugInfo	Change argument order and add explanatory comment to r206130	2014-04-14 22:23:06 +00:00
ExecutionEngine
Feature
FileCheck
Instrumentation
Integer
JitListener
Linker
LTO
MC	COFF: fix an off by one error	2014-04-16 06:22:53 +00:00
Object	[yaml2obj][ELF] ELF Relocations Support.	2014-04-11 04:13:39 +00:00
Other	Add -pass-remarks flag to 'opt'.	2014-04-08 16:42:38 +00:00
TableGen
tools	tools: fix invalid printing, buffer overrun in llvm-readobj	2014-04-16 04:15:29 +00:00
Transforms	Add lifetime markers for allocas created to hold byval arguments, make them	2014-04-15 18:06:46 +00:00
Unit
Verifier
YAMLParser
.clang-format
CMakeLists.txt
lit.cfg
lit.site.cfg.in
Makefile
Makefile.tests
TestRunner.sh