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https://github.com/jeremysrand/llvm-65816.git
synced 2024-06-07 19:29:33 +00:00
More infrastructure required for the basic function which returns a constant integer.
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@ -53,7 +53,7 @@ Here are the steps to checkout the code and build it:
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$ git clone https://github.com/jeremysrand/llvm-65816.git
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$ git clone https://github.com/jeremysrand/llvm-65816.git
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$ mkdir build
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$ mkdir build
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$ cd build
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$ cd build
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$ cmake -G "Unix Makefiles" ../llvm-65816
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$ cmake -DCMAKE_BUILD_TYPE:STRING=Debug -G "Unix Makefiles" ../llvm-65816
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$ make
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$ make
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That works for me on my Mac. Note, you probably need to download cmake.
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That works for me on my Mac. Note, you probably need to download cmake.
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@ -167,13 +167,13 @@ bool SparcDAGToDAGISel::SelectADDRrr(SDValue Addr, SDValue &R1, SDValue &R2) {
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#endif
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#endif
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SDNode *WDC65816DAGToDAGISel::Select(SDNode *N) {
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SDNode *WDC65816DAGToDAGISel::Select(SDNode *N) {
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WDC_LOG("WDC_TODO - Unimplemented method called, opcode=" << N);
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SDLoc dl(N);
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SDLoc dl(N);
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if (N->isMachineOpcode()) {
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if (N->isMachineOpcode()) {
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N->setNodeId(-1);
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N->setNodeId(-1);
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return NULL; // Already selected.
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return NULL; // Already selected.
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}
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}
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WDC_LOG("WDC_TODO - Unimplemented method called, opcode=" << N->getOpcode());
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switch (N->getOpcode()) {
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switch (N->getOpcode()) {
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default: break;
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default: break;
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@ -810,12 +810,16 @@ static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
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WDC65816TargetLowering::WDC65816TargetLowering(TargetMachine &TM)
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WDC65816TargetLowering::WDC65816TargetLowering(TargetMachine &TM)
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: TargetLowering(TM, new TargetLoweringObjectFileELF()) {
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: TargetLowering(TM, new TargetLoweringObjectFileELF()) {
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addRegisterClass(MVT::i16, &WDC::Int16RegsRegClass);
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addRegisterClass(MVT::i16, &WDC::AccRegsRegClass);
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addRegisterClass(MVT::i16, &WDC::IndexXRegsRegClass);
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addRegisterClass(MVT::i16, &WDC::IndexYRegsRegClass);
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#if 0 // WDC_TODO - turn these off for now...
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#if 0 // WDC_TODO - turn these off for now...
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// The problem here is that if LLVM thinks we have 32bit and 64bit registers
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// The problem here is that if LLVM thinks we have 32bit and 64bit registers
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// then it insists on promoting ints to 32-bit even though we have said we are
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// then it insists on promoting ints to 32-bit even though we have said we are
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// natively a 16-bit machine. Also, I haven't bothered to tell LLVM yet how to
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// natively a 16-bit machine. Also, I haven't bothered to tell LLVM yet how to
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// load values into these registers which I think confuses it. So, off for now.
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// load values into these registers which I think confuses it. So, off for now.
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addRegisterClass(MVT::i16, &WDC::Int16RegsRegClass);
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addRegisterClass(MVT::i32, &WDC::Int32RegsRegClass);
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addRegisterClass(MVT::i32, &WDC::Int32RegsRegClass);
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addRegisterClass(MVT::i64, &WDC::Int64RegsRegClass);
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addRegisterClass(MVT::i64, &WDC::Int64RegsRegClass);
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addRegisterClass(MVT::f32, &WDC::Float32RegsRegClass);
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addRegisterClass(MVT::f32, &WDC::Float32RegsRegClass);
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@ -64,3 +64,49 @@ unsigned WDC65816InstrInfo::getGlobalBaseReg(MachineFunction *MF) const
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return GlobalBaseReg;
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return GlobalBaseReg;
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#endif
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#endif
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}
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}
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void WDC65816InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill, int FrameIdx,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo &MFI = *MF.getFrameInfo();
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MachineMemOperand *MMO =
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MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
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MachineMemOperand::MOStore,
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MFI.getObjectSize(FrameIdx),
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MFI.getObjectAlignment(FrameIdx));
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if (RC == &WDC::AccRegsRegClass)
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BuildMI(MBB, MI, DL, get(WDC::STAabsl))
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.addFrameIndex(FrameIdx).addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
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else
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llvm_unreachable("Cannot store this register to stack slot!");
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}
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void WDC65816InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const{
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DebugLoc DL;
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo &MFI = *MF.getFrameInfo();
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MachineMemOperand *MMO =
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MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
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MachineMemOperand::MOLoad,
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MFI.getObjectSize(FrameIdx),
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MFI.getObjectAlignment(FrameIdx));
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if (RC == &WDC::AccRegsRegClass)
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BuildMI(MBB, MI, DL, get(WDC::LDAabsl))
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.addReg(DestReg).addFrameIndex(FrameIdx).addMemOperand(MMO);
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else
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llvm_unreachable("Cannot store this register to stack slot!");
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}
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@ -37,6 +37,18 @@ namespace llvm {
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unsigned getGlobalBaseReg(MachineFunction *MF) const;
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unsigned getGlobalBaseReg(MachineFunction *MF) const;
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virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill,
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int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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};
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};
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}
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}
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@ -30,12 +30,6 @@
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using namespace llvm;
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using namespace llvm;
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#if 0 // TODO - What is this?
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static cl::opt<bool>
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ReserveAppRegisters("sparc-reserve-app-registers", cl::Hidden, cl::init(false),
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cl::desc("Reserve application registers (%g2-%g4)"));
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#endif
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WDC65816RegisterInfo::WDC65816RegisterInfo(WDC65816Subtarget &st)
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WDC65816RegisterInfo::WDC65816RegisterInfo(WDC65816Subtarget &st)
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: WDC65816GenRegisterInfo(WDC::P), Subtarget(st) {
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: WDC65816GenRegisterInfo(WDC::P), Subtarget(st) {
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}
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}
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