2018-03-05 11:05:37 +00:00
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2018-07-12 16:30:35 +00:00
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#if not(ARCH_6502)
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#warn zp_reg module should be used only on 6502-compatible targets
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#endif
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2018-12-19 00:09:27 +00:00
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noinline asm byte __mul_u8u8u8() {
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2018-03-05 11:05:37 +00:00
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? LDA #0
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2018-06-18 20:40:32 +00:00
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? JMP __mul_u8u8u8_start
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__mul_u8u8u8_add:
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2018-07-01 17:07:47 +00:00
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? CLC
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2019-06-28 15:57:26 +00:00
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? ADC __reg
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2018-06-18 20:40:32 +00:00
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__mul_u8u8u8_loop:
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2019-06-28 15:57:26 +00:00
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? ASL __reg
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2018-06-18 20:40:32 +00:00
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__mul_u8u8u8_start:
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2019-06-28 15:57:26 +00:00
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? LSR __reg+1
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2018-07-01 17:07:47 +00:00
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? BCS __mul_u8u8u8_add
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? BNE __mul_u8u8u8_loop
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2018-03-05 11:05:37 +00:00
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? RTS
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}
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2018-12-14 21:50:20 +00:00
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2019-06-05 23:17:34 +00:00
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// divide __reg[0]/__reg[1]
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noinline asm byte __mod_u8u8u8u8() {
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? LDA #0
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? LDX #7
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? CLC
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__divmod_u8u8u8u8_start:
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2019-06-28 15:57:26 +00:00
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? ROL __reg
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2019-06-05 23:17:34 +00:00
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? ROL
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2019-06-28 15:57:26 +00:00
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? CMP __reg+1
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2019-06-05 23:17:34 +00:00
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? BCC __divmod_u8u8u8u8_skip
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2019-06-28 15:57:26 +00:00
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? SBC __reg+1
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2019-06-05 23:17:34 +00:00
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__divmod_u8u8u8u8_skip:
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? DEX
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? BPL __divmod_u8u8u8u8_start
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2019-06-28 15:57:26 +00:00
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? ROL __reg
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2019-06-05 23:17:34 +00:00
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? RTS
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}
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asm byte __div_u8u8u8u8() {
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? JSR __mod_u8u8u8u8
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2019-06-28 15:57:26 +00:00
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? LDA __reg
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2019-06-05 23:17:34 +00:00
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? RTS
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}
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2018-12-14 21:50:20 +00:00
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#if ZPREG_SIZE >= 3
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2018-12-19 00:09:27 +00:00
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noinline asm word __mul_u16u8u16() {
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2018-12-14 21:50:20 +00:00
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? LDA #0
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? TAX
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? JMP __mul_u16u8u16_start
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__mul_u16u8u16_add:
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? CLC
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2019-06-28 15:57:26 +00:00
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? ADC __reg
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2018-12-14 21:50:20 +00:00
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? TAY
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? TXA
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2019-06-28 15:57:26 +00:00
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? ADC __reg+1
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2018-12-14 21:50:20 +00:00
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? TAX
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? TYA
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__mul_u16u8u16_loop:
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2019-06-28 15:57:26 +00:00
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? ASL __reg
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? ROL __reg+1
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2018-12-14 21:50:20 +00:00
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__mul_u16u8u16_start:
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2019-06-28 15:57:26 +00:00
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? LSR __reg+2
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2018-12-14 21:50:20 +00:00
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? BCS __mul_u16u8u16_add
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? BNE __mul_u16u8u16_loop
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? RTS
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}
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2019-06-06 11:06:30 +00:00
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// divide (__reg[1]:__reg[0])/__reg[2]
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2019-08-03 21:58:47 +00:00
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// remainder in A, quotient in (__reg[1]:__reg[0])
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2019-06-06 11:06:30 +00:00
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noinline asm byte __mod_u16u8u16u8() {
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? LDX #15
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? CLC
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2019-08-03 21:58:47 +00:00
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// TODO: decide when
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#if OPTIMIZE_FOR_SPEED
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? LDA __reg+2
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? BMI __divmod_u16u8u16u8_variant2
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? LDA #0
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__divmod_u16u8u16u8_start: // for divisors <= 127
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2019-06-28 15:57:26 +00:00
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? ROL __reg
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? ROL __reg+1
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2019-06-06 11:06:30 +00:00
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? ROL
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2019-06-28 15:57:26 +00:00
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? CMP __reg+2
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2019-06-06 11:06:30 +00:00
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? BCC __divmod_u16u8u16u8_skip
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2019-06-28 15:57:26 +00:00
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? SBC __reg+2
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2019-06-06 11:06:30 +00:00
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__divmod_u16u8u16u8_skip:
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? DEX
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? BPL __divmod_u16u8u16u8_start
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2019-06-28 15:57:26 +00:00
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? ROL __reg
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? ROL __reg+1
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2019-06-06 11:06:30 +00:00
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? RTS
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2019-08-03 21:58:47 +00:00
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#endif
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__divmod_u16u8u16u8_variant2:
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? LDA #0
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__divmod_u16u8u16u8_start2: // for divisors >= 128
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? ROL __reg
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? ROL __reg+1
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? ROL
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? BCS __divmod_u16u8u16u8_sub2
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? CMP __reg+2
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? BCC __divmod_u16u8u16u8_skip2
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__divmod_u16u8u16u8_sub2:
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? SBC __reg+2
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? SEC
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__divmod_u16u8u16u8_skip2:
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? DEX
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? BPL __divmod_u16u8u16u8_start2
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? ROL __reg
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? ROL __reg+1
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? RTS
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2019-06-06 11:06:30 +00:00
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}
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asm word __div_u16u8u16u8() {
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? JSR __mod_u16u8u16u8
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2019-06-28 15:57:26 +00:00
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? LDA __reg
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? LDX __reg+1
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2019-06-06 11:06:30 +00:00
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? RTS
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2019-08-03 21:58:47 +00:00
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2019-06-06 11:06:30 +00:00
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}
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2018-12-14 21:50:20 +00:00
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#endif
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2019-07-26 22:58:10 +00:00
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#if ZPREG_SIZE >= 4
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noinline asm word call(word ax) {
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JMP ((__reg + 2))
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}
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2019-09-04 19:17:06 +00:00
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noinline asm word __mul_u16u16u16() {
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#if ZPREG_SIZE < 6
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? LDA __reg+1
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? PHA
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? LDA __reg
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? PHA
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? TSX
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#else
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? LDA __reg
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? STA __reg+4
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? LDA __reg+1
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? STA __reg+5
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#endif
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#if CPUFEATURE_65C02 && not(CPUFEATURE_65CE02)
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? STZ __reg
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? STZ __reg+1
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#else
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? LDA #0
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? STA __reg
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? STA __reg+1
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#endif
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? LDY #16
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__mul_u16u16u32_loop:
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? ASL __reg
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? ROL __reg+1
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? ROL __reg+2
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? ROL __reg+3
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? BCC __mul_u16u16u32_skip
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#if ZPREG_SIZE < 6
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? LDA $101,X
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#else
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? LDA __reg+4
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#endif
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? CLC
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? ADC __reg
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? STA __reg
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#if ZPREG_SIZE < 6
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? LDA $102,X
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#else
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? LDA __reg+5
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#endif
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? ADC __reg+1
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? STA __reg+1
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? BCC __mul_u16u16u32_skip
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? INC __reg+2
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__mul_u16u16u32_skip:
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? DEY
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? BNE __mul_u16u16u32_loop
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#if ZPREG_SIZE < 6
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#if OPTIMIZE_FOR_SPEED
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? INX
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? INX
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? TXS
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#else
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? PLA
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? PLA
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#endif
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#endif
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? LDA __reg
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? LDX __reg+1
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? RTS
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}
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// divide (__reg[1]:__reg[0])/(__reg[3]:__reg[2])
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// remainder in (__reg[2]:__reg[3]), quotient in (__reg[1]:__reg[0])
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noinline asm word __divmod_u16u16u16u16() {
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#if ZPREG_SIZE < 6
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? LDA __reg+3
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? PHA
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? LDA __reg+2
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? PHA
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? TSX
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#else
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? LDA __reg+2
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? STA __reg+4
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? LDA __reg+3
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? STA __reg+5
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#endif
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#if CPUFEATURE_65C02 && not(CPUFEATURE_65CE02)
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? STZ __reg+2
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? STZ __reg+3
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#else
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? LDA #0
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? STA __reg+2
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? STA __reg+3
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#endif
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#if ZPREG_SIZE < 6
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? LDA #16
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? PHA
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#else
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? LDX #16
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#endif
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__divmod_u16u16u16u16_loop:
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? ASL __reg
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? ROL __reg+1
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? ROL __reg+2
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? ROL __reg+3
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? LDA __reg+2
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sec
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#if ZPREG_SIZE < 6
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? SBC $102,X
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#else
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? SBC __reg+4
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#endif
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? TAY
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? LDA __reg+3
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#if ZPREG_SIZE < 6
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? SBC $103,X
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#else
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? SBC __reg+5
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#endif
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? BCC __divmod_u16u16u16u16_skip
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? STA __reg+3
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? STY __reg+2
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? INC __reg
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__divmod_u16u16u16u16_skip:
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#if ZPREG_SIZE < 6
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? DEC $101,X
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#else
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? DEX
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#endif
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? BNE __divmod_u16u16u16u16_loop
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#if ZPREG_SIZE < 6
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#if OPTIMIZE_FOR_SIZE
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? PLA
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? PLA
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? PLA
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#else
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? INX
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? INX
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? INX
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? TXS
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#endif
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#endif
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? RTS
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}
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asm word __div_u16u16u16u16() {
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JSR __divmod_u16u16u16u16
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? LDA __reg
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? LDX __reg+1
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? RTS
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}
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asm word __mod_u16u16u16u16() {
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JSR __divmod_u16u16u16u16
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? LDA __reg+2
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? LDX __reg+3
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? RTS
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}
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2019-07-26 22:58:10 +00:00
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#endif
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