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Z80: Fix SET n,(IX+d) and related instructions

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This commit is contained in:
Karol Stasiak 2018-07-24 20:13:29 +02:00
parent 71ad93fe09
commit 1e822239d0
1 changed files with 4 additions and 3 deletions
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7
src/main/scala/millfork/output/Z80Assembler.scala
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@ -159,8 +159,8 @@ class Z80Assembler(program: Program,
case ZLine(op, OneRegisterOffset(ix@(ZRegister.MEM_IX_D | ZRegister.MEM_IY_D), offset), _, _) if ZOpcodeClasses.AllSingleBit(op) =>
writeByte(bank, index, prefixByte(ix))
writeByte(bank, index + 1, 0xcb)
writeByte(bank, index + 2, ZOpcodeClasses.singleBitOpcode(op) + internalRegisterIndex(ZRegister.MEM_HL))
writeByte(bank, index + 3, offset)
writeByte(bank, index + 2, offset)
writeByte(bank, index + 3, ZOpcodeClasses.singleBitOpcode(op) + internalRegisterIndex(ZRegister.MEM_HL))
index + 4
case ZLine(op, OneRegisterOffset(ix@(ZRegister.MEM_IX_D | ZRegister.MEM_IY_D), offset), _, _) if oneRegister.contains(op) =>
val o = oneRegister(op)
@ -191,7 +191,8 @@ class Z80Assembler(program: Program,
writeByte(bank, index, prefixByte(ix))
writeByte(bank, index + 1, 0xcb)
writeByte(bank, index + 2, offset)
index + 3
writeByte(bank, index + 3, o.opcode + internalRegisterIndex(MEM_HL) * o.multiplier)
index + 4
case ZLine(LD, registers, _, _) =>
registers match {
case TwoRegisters(I, A) =>