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Z80: optimize loads to registers pairs

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This commit is contained in:
Karol Stasiak 2018-08-07 17:35:02 +02:00
parent a8f6bc4c0e
commit 3e7bbaf5fc
1 changed files with 45 additions and 0 deletions
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45
src/main/scala/millfork/assembly/z80/opt/AlwaysGoodI80Optimizations.scala
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@ -527,6 +527,36 @@ object AlwaysGoodI80Optimizations {
(Elidable & HasOpcode(OR) & HasRegisterParam(A) & DoesntMatterWhatItDoesWithFlags) ~~> (_ => Nil),
(Elidable & HasOpcode(LD_16) & HasRegisters(TwoRegisters(HL, IMM_16)) & MatchParameter(0)) ~
(Elidable & HasOpcode(INC_16) & HasRegisterParam(HL) & DoesntMatterWhatItDoesWithFlagsExceptCarry) ~~> { (_, ctx) =>
List(ZLine.ldImm16(HL, ctx.get[Constant](0).+(1).quickSimplify))
},
(Elidable & HasOpcode(LD_16) & HasRegisters(TwoRegisters(HL, IMM_16)) & MatchParameter(0)) ~
(Elidable & HasOpcode(DEC_16) & HasRegisterParam(HL) & DoesntMatterWhatItDoesWithFlagsExceptCarry) ~~> { (_, ctx) =>
List(ZLine.ldImm16(HL, ctx.get[Constant](0).+(1).quickSimplify))
},
(Elidable & HasOpcode(LD_16) & HasRegisters(TwoRegisters(DE, IMM_16)) & MatchParameter(0)) ~
(Elidable & HasOpcode(INC_16) & HasRegisterParam(DE) & DoesntMatterWhatItDoesWithFlagsExceptCarry) ~~> { (_, ctx) =>
List(ZLine.ldImm16(DE, ctx.get[Constant](0).+(1).quickSimplify))
},
(Elidable & HasOpcode(LD_16) & HasRegisters(TwoRegisters(DE, IMM_16)) & MatchParameter(0)) ~
(Elidable & HasOpcode(DEC_16) & HasRegisterParam(DE) & DoesntMatterWhatItDoesWithFlagsExceptCarry) ~~> { (_, ctx) =>
List(ZLine.ldImm16(DE, ctx.get[Constant](0).-(1).quickSimplify))
},
(Elidable & HasOpcode(LD_16) & HasRegisters(TwoRegisters(BC, IMM_16)) & MatchParameter(0)) ~
(Elidable & HasOpcode(INC_16) & HasRegisterParam(BC) & DoesntMatterWhatItDoesWithFlagsExceptCarry) ~~> { (_, ctx) =>
List(ZLine.ldImm16(BC, ctx.get[Constant](0).+(1).quickSimplify))
},
(Elidable & HasOpcode(LD_16) & HasRegisters(TwoRegisters(BC, IMM_16)) & MatchParameter(0)) ~
(Elidable & HasOpcode(DEC_16) & HasRegisterParam(BC) & DoesntMatterWhatItDoesWithFlagsExceptCarry) ~~> { (_, ctx) =>
List(ZLine.ldImm16(BC, ctx.get[Constant](0).-(1).quickSimplify))
},
)
val FreeHL = new RuleBasedAssemblyOptimization("Free HL",
@ -714,6 +744,21 @@ object AlwaysGoodI80Optimizations {
(Elidable & HasOpcode(ADD_16) & HasRegisters(TwoRegisters(ZRegister.HL, ZRegister.BC)) & DoesntMatterWhatItDoesWith(ZRegister.DE, ZRegister.BC)) ~~> { code =>
code.drop(2).init :+ code.last.copy(registers = TwoRegisters(ZRegister.HL, ZRegister.DE))
},
(Elidable & Is8BitLoadTo(ZRegister.H) & MatchImmediate(1)) ~
(Elidable & Is8BitLoadTo(ZRegister.L) & MatchImmediate(0)) ~~> { (code, ctx) =>
List(ZLine.ldImm16(ZRegister.HL, (ctx.get[Constant](0) + ctx.get[Constant](1).asl(8)).quickSimplify))
},
(Elidable & Is8BitLoadTo(ZRegister.D) & MatchImmediate(1)) ~
(Elidable & Is8BitLoadTo(ZRegister.E) & MatchImmediate(0)) ~~> { (code, ctx) =>
List(ZLine.ldImm16(ZRegister.DE, (ctx.get[Constant](0) + ctx.get[Constant](1).asl(8)).quickSimplify))
},
(Elidable & Is8BitLoadTo(ZRegister.B) & MatchImmediate(1)) ~
(Elidable & Is8BitLoadTo(ZRegister.C) & MatchImmediate(0)) ~~> { (code, ctx) =>
List(ZLine.ldImm16(ZRegister.BC, (ctx.get[Constant](0) + ctx.get[Constant](1).asl(8)).quickSimplify))
},
)
val UnusedCodeRemoval = new RuleBasedAssemblyOptimization("Unreachable code removal",