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6502: Fix some optimizations

This commit is contained in:
Karol Stasiak 2018-12-27 20:46:50 +01:00
parent e0cc25c54f
commit 985663083a
2 changed files with 16 additions and 6 deletions

View File

@ -1923,25 +1923,25 @@ object AlwaysGoodOptimizations {
needsFlowInfo = FlowInfoRequirement.JustLabels, needsFlowInfo = FlowInfoRequirement.JustLabels,
(HasOpcode(LABEL) & MatchParameter(2) & HasCallerCount(1)) ~ (HasOpcode(LABEL) & MatchParameter(2) & HasCallerCount(1)) ~
(Elidable & HasOpcode(LDA) & MatchAddrMode(0) & MatchParameter(1) & IsNonvolatile) ~ (Elidable & HasOpcode(LDA) & MatchAddrMode(0) & MatchParameter(1) & IsNonvolatile) ~
(Linear & Not(ChangesA) & DoesntChangeMemoryAt(0, 1)).* ~ (Linear & Not(ChangesA) & DoesntChangeMemoryAt(0, 1) & DoesntChangeIndexingInAddrMode(0)).* ~
(ShortConditionalBranching & MatchParameter(2)) ~~> { code => (ShortConditionalBranching & MatchParameter(2)) ~~> { code =>
code(1) :: code(0) :: code.drop(2) code(1) :: code(0) :: code.drop(2)
}, },
(HasOpcode(LABEL) & MatchParameter(2) & HasCallerCount(1)) ~ (HasOpcode(LABEL) & MatchParameter(2) & HasCallerCount(1)) ~
(Elidable & HasOpcode(LDX) & MatchAddrMode(0) & MatchParameter(1) & IsNonvolatile) ~ (Elidable & HasOpcode(LDX) & MatchAddrMode(0) & MatchParameter(1) & IsNonvolatile) ~
(Linear & Not(ChangesX) & DoesntChangeMemoryAt(0, 1)).* ~ (Linear & Not(ChangesX) & DoesntChangeMemoryAt(0, 1) & DoesntChangeIndexingInAddrMode(0)).* ~
(ShortConditionalBranching & MatchParameter(2)) ~~> { code => (ShortConditionalBranching & MatchParameter(2)) ~~> { code =>
code(1) :: code(0) :: code.drop(2) code(1) :: code(0) :: code.drop(2)
}, },
(HasOpcode(LABEL) & MatchParameter(2) & HasCallerCount(1)) ~ (HasOpcode(LABEL) & MatchParameter(2) & HasCallerCount(1)) ~
(Elidable & HasOpcode(LDY) & MatchAddrMode(0) & MatchParameter(1) & IsNonvolatile) ~ (Elidable & HasOpcode(LDY) & MatchAddrMode(0) & MatchParameter(1) & IsNonvolatile) ~
(Linear & Not(ChangesY) & DoesntChangeMemoryAt(0, 1)).* ~ (Linear & Not(ChangesY) & DoesntChangeMemoryAt(0, 1) & DoesntChangeIndexingInAddrMode(0)).* ~
(ShortConditionalBranching & MatchParameter(2)) ~~> { code => (ShortConditionalBranching & MatchParameter(2)) ~~> { code =>
code(1) :: code(0) :: code.drop(2) code(1) :: code(0) :: code.drop(2)
}, },
(HasOpcode(LABEL) & MatchParameter(2) & HasCallerCount(1)) ~ (HasOpcode(LABEL) & MatchParameter(2) & HasCallerCount(1)) ~
(Elidable & HasOpcode(LDZ) & MatchAddrMode(0) & MatchParameter(1)) ~ (Elidable & HasOpcode(LDZ) & MatchAddrMode(0) & MatchParameter(1)) ~
(Linear & Not(ChangesIZ) & DoesntChangeMemoryAt(0, 1)).* ~ (Linear & Not(ChangesIZ) & DoesntChangeMemoryAt(0, 1) & DoesntChangeIndexingInAddrMode(0)).* ~
(ShortConditionalBranching & MatchParameter(2)) ~~> { code => (ShortConditionalBranching & MatchParameter(2)) ~~> { code =>
code(1) :: code(0) :: code.drop(2) code(1) :: code(0) :: code.drop(2)
}, },
@ -2659,5 +2659,15 @@ object AlwaysGoodOptimizations {
code(3).copy(opcode = BCC)) code(3).copy(opcode = BCC))
}, },
(Elidable & HasOpcode(TXA)) ~
(Elidable & HasOpcode(CMP) & DoesntMatterWhatItDoesWith(State.A) & HasAddrModeIn(Absolute, ZeroPage, Immediate)) ~~> { code =>
List(code.last.copy(opcode = CPX))
},
(Elidable & HasOpcode(TYA)) ~
(Elidable & HasOpcode(CMP) & DoesntMatterWhatItDoesWith(State.A) & HasAddrModeIn(Absolute, ZeroPage, Immediate)) ~~> { code =>
List(code.last.copy(opcode = CPY))
},
) )
} }

View File

@ -52,7 +52,7 @@ object VariableToRegisterOptimization extends AssemblyOptimization[AssemblyLine]
private val opcodesThatAlwaysPrecludeXAllocation = Set( private val opcodesThatAlwaysPrecludeXAllocation = Set(
JSR, STX, TXA, INX, DEX, CPX, JSR, STX, TXA, INX, DEX, CPX,
LDX_W, STX_W, CPX_W, DEX_W, INX_W, LDX_W, STX_W, CPX_W, DEX_W, INX_W,
PHX, PLX, PHX, PLX, PHX_W, PLX_W,
SBX, SAX, LXA, XAA, AHX, SHX, SHY, LAS, TAS, SBX, SAX, LXA, XAA, AHX, SHX, SHY, LAS, TAS,
HuSAX, SXY, TXY, TXY, HuSAX, SXY, TXY, TXY,
BYTE, BYTE,
@ -61,7 +61,7 @@ object VariableToRegisterOptimization extends AssemblyOptimization[AssemblyLine]
private val opcodesThatAlwaysPrecludeYAllocation = Set( private val opcodesThatAlwaysPrecludeYAllocation = Set(
JSR, STY, TYA, INY, DEY, CPY, JSR, STY, TYA, INY, DEY, CPY,
LDY_W, STY_W, CPY_W, DEY_W, INY_W, LDY_W, STY_W, CPY_W, DEY_W, INY_W,
PHY, PLY, PHY, PLY, PHY_W, PLY_W,
AHX, SHX, SHY, LAS, TAS, AHX, SHX, SHY, LAS, TAS,
SAY, SXY, TXY, TYX, SAY, SXY, TXY, TYX,
BYTE, BYTE,