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6502: Fix some optimizations
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parent
e0cc25c54f
commit
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@ -1923,25 +1923,25 @@ object AlwaysGoodOptimizations {
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needsFlowInfo = FlowInfoRequirement.JustLabels,
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needsFlowInfo = FlowInfoRequirement.JustLabels,
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(HasOpcode(LABEL) & MatchParameter(2) & HasCallerCount(1)) ~
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(HasOpcode(LABEL) & MatchParameter(2) & HasCallerCount(1)) ~
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(Elidable & HasOpcode(LDA) & MatchAddrMode(0) & MatchParameter(1) & IsNonvolatile) ~
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(Elidable & HasOpcode(LDA) & MatchAddrMode(0) & MatchParameter(1) & IsNonvolatile) ~
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(Linear & Not(ChangesA) & DoesntChangeMemoryAt(0, 1)).* ~
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(Linear & Not(ChangesA) & DoesntChangeMemoryAt(0, 1) & DoesntChangeIndexingInAddrMode(0)).* ~
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(ShortConditionalBranching & MatchParameter(2)) ~~> { code =>
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(ShortConditionalBranching & MatchParameter(2)) ~~> { code =>
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code(1) :: code(0) :: code.drop(2)
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code(1) :: code(0) :: code.drop(2)
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},
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},
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(HasOpcode(LABEL) & MatchParameter(2) & HasCallerCount(1)) ~
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(HasOpcode(LABEL) & MatchParameter(2) & HasCallerCount(1)) ~
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(Elidable & HasOpcode(LDX) & MatchAddrMode(0) & MatchParameter(1) & IsNonvolatile) ~
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(Elidable & HasOpcode(LDX) & MatchAddrMode(0) & MatchParameter(1) & IsNonvolatile) ~
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(Linear & Not(ChangesX) & DoesntChangeMemoryAt(0, 1)).* ~
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(Linear & Not(ChangesX) & DoesntChangeMemoryAt(0, 1) & DoesntChangeIndexingInAddrMode(0)).* ~
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(ShortConditionalBranching & MatchParameter(2)) ~~> { code =>
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(ShortConditionalBranching & MatchParameter(2)) ~~> { code =>
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code(1) :: code(0) :: code.drop(2)
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code(1) :: code(0) :: code.drop(2)
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},
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},
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(HasOpcode(LABEL) & MatchParameter(2) & HasCallerCount(1)) ~
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(HasOpcode(LABEL) & MatchParameter(2) & HasCallerCount(1)) ~
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(Elidable & HasOpcode(LDY) & MatchAddrMode(0) & MatchParameter(1) & IsNonvolatile) ~
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(Elidable & HasOpcode(LDY) & MatchAddrMode(0) & MatchParameter(1) & IsNonvolatile) ~
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(Linear & Not(ChangesY) & DoesntChangeMemoryAt(0, 1)).* ~
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(Linear & Not(ChangesY) & DoesntChangeMemoryAt(0, 1) & DoesntChangeIndexingInAddrMode(0)).* ~
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(ShortConditionalBranching & MatchParameter(2)) ~~> { code =>
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(ShortConditionalBranching & MatchParameter(2)) ~~> { code =>
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code(1) :: code(0) :: code.drop(2)
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code(1) :: code(0) :: code.drop(2)
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},
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},
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(HasOpcode(LABEL) & MatchParameter(2) & HasCallerCount(1)) ~
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(HasOpcode(LABEL) & MatchParameter(2) & HasCallerCount(1)) ~
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(Elidable & HasOpcode(LDZ) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Elidable & HasOpcode(LDZ) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Linear & Not(ChangesIZ) & DoesntChangeMemoryAt(0, 1)).* ~
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(Linear & Not(ChangesIZ) & DoesntChangeMemoryAt(0, 1) & DoesntChangeIndexingInAddrMode(0)).* ~
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(ShortConditionalBranching & MatchParameter(2)) ~~> { code =>
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(ShortConditionalBranching & MatchParameter(2)) ~~> { code =>
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code(1) :: code(0) :: code.drop(2)
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code(1) :: code(0) :: code.drop(2)
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},
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},
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@ -2659,5 +2659,15 @@ object AlwaysGoodOptimizations {
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code(3).copy(opcode = BCC))
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code(3).copy(opcode = BCC))
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},
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},
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(Elidable & HasOpcode(TXA)) ~
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(Elidable & HasOpcode(CMP) & DoesntMatterWhatItDoesWith(State.A) & HasAddrModeIn(Absolute, ZeroPage, Immediate)) ~~> { code =>
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List(code.last.copy(opcode = CPX))
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},
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(Elidable & HasOpcode(TYA)) ~
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(Elidable & HasOpcode(CMP) & DoesntMatterWhatItDoesWith(State.A) & HasAddrModeIn(Absolute, ZeroPage, Immediate)) ~~> { code =>
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List(code.last.copy(opcode = CPY))
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},
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)
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)
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}
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}
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@ -52,7 +52,7 @@ object VariableToRegisterOptimization extends AssemblyOptimization[AssemblyLine]
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private val opcodesThatAlwaysPrecludeXAllocation = Set(
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private val opcodesThatAlwaysPrecludeXAllocation = Set(
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JSR, STX, TXA, INX, DEX, CPX,
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JSR, STX, TXA, INX, DEX, CPX,
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LDX_W, STX_W, CPX_W, DEX_W, INX_W,
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LDX_W, STX_W, CPX_W, DEX_W, INX_W,
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PHX, PLX,
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PHX, PLX, PHX_W, PLX_W,
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SBX, SAX, LXA, XAA, AHX, SHX, SHY, LAS, TAS,
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SBX, SAX, LXA, XAA, AHX, SHX, SHY, LAS, TAS,
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HuSAX, SXY, TXY, TXY,
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HuSAX, SXY, TXY, TXY,
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BYTE,
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BYTE,
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@ -61,7 +61,7 @@ object VariableToRegisterOptimization extends AssemblyOptimization[AssemblyLine]
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private val opcodesThatAlwaysPrecludeYAllocation = Set(
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private val opcodesThatAlwaysPrecludeYAllocation = Set(
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JSR, STY, TYA, INY, DEY, CPY,
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JSR, STY, TYA, INY, DEY, CPY,
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LDY_W, STY_W, CPY_W, DEY_W, INY_W,
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LDY_W, STY_W, CPY_W, DEY_W, INY_W,
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PHY, PLY,
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PHY, PLY, PHY_W, PLY_W,
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AHX, SHX, SHY, LAS, TAS,
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AHX, SHX, SHY, LAS, TAS,
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SAY, SXY, TXY, TYX,
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SAY, SXY, TXY, TYX,
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BYTE,
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BYTE,
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