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trb tsb
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2a2ab1eadd
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32
src/cpu.rs
32
src/cpu.rs
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@ -653,6 +653,38 @@ impl<M: Bus, V: Variant> CPU<M, V> {
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let val = self.registers.accumulator;
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self.load_y_register(val);
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}
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(Instruction::TRB, OpInput::UseAddress(addr)) => {
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let val = self.memory.get_byte(addr);
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// The zero flag is set based on the result of the 'and'.
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self.registers.status.set_with_mask(
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Status::PS_ZERO,
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Status::new(StatusArgs {
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zero: 0 == (self.registers.accumulator & val),
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..StatusArgs::none()
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}),
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);
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// The 1's in the accumulator set the corresponding bits in the operand
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let res = self.registers.accumulator | val;
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self.memory.set_byte(addr, res);
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}
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(Instruction::TSB, OpInput::UseAddress(addr)) => {
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let val = self.memory.get_byte(addr);
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// The zero flag is set based on the result of the 'and'.
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self.registers.status.set_with_mask(
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Status::PS_ZERO,
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Status::new(StatusArgs {
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zero: 0 == (self.registers.accumulator & val),
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..StatusArgs::none()
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}),
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);
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// The 1's in the accumulator clear the corresponding bits in the operand
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let res = (self.registers.accumulator ^ 0xff) & val;
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self.memory.set_byte(addr, res);
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}
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(Instruction::TSX, OpInput::UseImplied) => {
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let StackPointer(val) = self.registers.stack_pointer;
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self.load_x_register(val);
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@ -210,6 +210,12 @@ pub enum Instruction {
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// Transfer Accumulator to Y
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TAY,
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// Test and Reset Bits
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TRB,
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// Test and Set Bits
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TSB,
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// Transfer Stack pointer to X
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TSX,
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@ -623,6 +629,10 @@ impl crate::Variant for Cmos6502 {
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0xfa => Some((Instruction::PLX, AddressingMode::Implied)),
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0x5a => Some((Instruction::PHY, AddressingMode::Implied)),
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0xda => Some((Instruction::PHX, AddressingMode::Implied)),
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0x04 => Some((Instruction::TSB, AddressingMode::ZeroPage)),
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0x14 => Some((Instruction::TRB, AddressingMode::ZeroPage)),
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0x0c => Some((Instruction::TSB, AddressingMode::Absolute)),
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0x1c => Some((Instruction::TRB, AddressingMode::Absolute)),
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_ => Nmos6502::decode(opcode),
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}
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}
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