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add Line6x mode for 240p/288p

This commit is contained in:
marqs 2023-08-23 21:34:40 +03:00
parent 31851f372d
commit 0ce2809183
12 changed files with 7293 additions and 7164 deletions
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33
rtl/scanconverter.v
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@ -83,7 +83,10 @@ localparam FID_EVEN = 1'b0;
localparam FID_ODD = 1'b1;
localparam PP_PL_START = 1;
localparam PP_LINEBUF_START = PP_PL_START + 1;
localparam PP_MASK_START = PP_PL_START;
localparam PP_MASK_LENGTH = 1;
localparam PP_MASK_END = PP_MASK_START + PP_MASK_LENGTH;
localparam PP_LINEBUF_START = PP_MASK_END;
localparam PP_LINEBUF_LENGTH = 1;
localparam PP_LINEBUF_END = PP_LINEBUF_START + PP_LINEBUF_LENGTH;
localparam PP_SRCSEL_START = PP_LINEBUF_END;
@ -188,7 +191,7 @@ reg VSYNC_pp[PP_PL_START:PP_PL_END] /* synthesis ramstyle = "logic" */;
reg DE_pp[PP_PL_START:PP_PL_END] /* synthesis ramstyle = "logic" */;
reg [11:0] xpos_pp[PP_PL_START:PP_PL_END] /* synthesis ramstyle = "logic" */;
reg [10:0] ypos_pp[PP_PL_START:PP_PL_END] /* synthesis ramstyle = "logic" */;
reg mask_enable_pp[PP_LINEBUF_START:PP_TP_START] /* synthesis ramstyle = "logic" */;
reg mask_enable_pp[PP_MASK_END:PP_TP_START] /* synthesis ramstyle = "logic" */;
reg draw_sl_pp[(PP_SLGEN_START+1):(PP_SLGEN_END-1)] /* synthesis ramstyle = "logic" */;
reg [7:0] sl_str_pp[(PP_SLGEN_START+1):(PP_SLGEN_START+2)] /* synthesis ramstyle = "logic" */;
reg [3:0] x_ctr_sl_pp[PP_PL_START:PP_SLGEN_START] /* synthesis ramstyle = "logic" */;
@ -394,7 +397,7 @@ always @(posedge PCLK_OUT_i) begin
if (~ext_sync_mode & ~MISC_LM_DEINT_MODE & (Y_RPT > 0) & ~V_INTERLACED & (src_fid == FID_EVEN)) begin
ypos_lb_next <= 11'(Y_START_LB) - 1'b1;
y_ctr <= ((Y_RPT+1'b1) >> 1);
y_ctr_sl_pp[1] <= SL_BOB_ALTERN ? ((Y_RPT+1'b1) >> 1) : 0;
y_ctr_sl_pp[1] <= SL_BOB_ALTERN ? ((Y_RPT+1'b1) >> 1) : '0;
end else begin
if (Y_SKIP & (dst_fid == FID_EVEN)) begin
// Linedrop mode and output interlaced
@ -427,7 +430,7 @@ always @(posedge PCLK_OUT_i) begin
y_ctr <= y_ctr + 1'b1;
end
if (!ypos_pp_init)
y_ctr_sl_pp[1] <= (y_ctr_sl_pp[1] == SL_IV_Y) ? 0 : y_ctr_sl_pp[1] + 1'b1;
y_ctr_sl_pp[1] <= (y_ctr_sl_pp[1] == SL_IV_Y) ? '0 : y_ctr_sl_pp[1] + 1'b1;
end
end
xpos_pp[1] <= 0;
@ -446,7 +449,7 @@ always @(posedge PCLK_OUT_i) begin
end else begin
x_ctr <= x_ctr + 1'b1;
end
x_ctr_sl_pp[1] <= (x_ctr_sl_pp[1] == SL_IV_X) ? 0 : x_ctr_sl_pp[1] + 1'b1;
x_ctr_sl_pp[1] <= (x_ctr_sl_pp[1] == SL_IV_X) ? '0 : x_ctr_sl_pp[1] + 1'b1;
end
end
end
@ -454,15 +457,14 @@ end
// Pipeline stages 2-
integer pp_idx;
always @(posedge PCLK_OUT_i) begin
for(pp_idx = PP_LINEBUF_START; pp_idx <= PP_PL_END; pp_idx = pp_idx+1) begin
for(pp_idx = PP_PL_START+1; pp_idx <= PP_PL_END; pp_idx = pp_idx+1) begin
HSYNC_pp[pp_idx] <= HSYNC_pp[pp_idx-1];
VSYNC_pp[pp_idx] <= VSYNC_pp[pp_idx-1];
DE_pp[pp_idx] <= DE_pp[pp_idx-1];
xpos_pp[pp_idx] <= xpos_pp[pp_idx-1];
ypos_pp[pp_idx] <= ypos_pp[pp_idx-1];
end
for(pp_idx = PP_LINEBUF_START; pp_idx <= PP_SLGEN_START; pp_idx = pp_idx+1) begin
for(pp_idx = PP_PL_START+1; pp_idx <= PP_SLGEN_START; pp_idx = pp_idx+1) begin
x_ctr_sl_pp[pp_idx] <= x_ctr_sl_pp[pp_idx-1];
y_ctr_sl_pp[pp_idx] <= y_ctr_sl_pp[pp_idx-1];
end
@ -473,16 +475,17 @@ always @(posedge PCLK_OUT_i) begin
B_pp[pp_idx] <= B_pp[pp_idx-1];
end
if (($signed({1'b0, xpos_pp[PP_LINEBUF_START-1]}) >= X_OFFSET) &
($signed({1'b0, xpos_pp[PP_LINEBUF_START-1]}) < X_OFFSET+X_SIZE) &
($signed({1'b0, ypos_pp[PP_LINEBUF_START-1]}) >= Y_OFFSET) &
($signed({1'b0, ypos_pp[PP_LINEBUF_START-1]}) < Y_OFFSET+Y_SIZE))
/* ---------- Mask enable calculation (1 cycle) ---------- */
if (($signed({1'b0, xpos_pp[PP_MASK_START]}) >= X_OFFSET) &
($signed({1'b0, xpos_pp[PP_MASK_START]}) < X_OFFSET+X_SIZE) &
($signed({1'b0, ypos_pp[PP_MASK_START]}) >= Y_OFFSET) &
($signed({1'b0, ypos_pp[PP_MASK_START]}) < Y_OFFSET+Y_SIZE))
begin
mask_enable_pp[PP_LINEBUF_START] <= 1'b0;
mask_enable_pp[PP_MASK_END] <= 1'b0;
end else begin
mask_enable_pp[PP_LINEBUF_START] <= 1'b1;
mask_enable_pp[PP_MASK_END] <= 1'b1;
end
for(pp_idx = PP_LINEBUF_START+1; pp_idx <= PP_TP_START; pp_idx = pp_idx+1) begin
for(pp_idx = PP_MASK_END+1; pp_idx <= PP_TP_START; pp_idx = pp_idx+1) begin
mask_enable_pp[pp_idx] <= mask_enable_pp[pp_idx-1];
end

2
rtl/tvp7002_frontend.v
View File

@ -62,7 +62,7 @@ localparam VSYNC_SEPARATED = 1'b0;
localparam VSYNC_RAW = 1'b1;
localparam PP_PL_START = 1;
localparam PP_RLPF_START = PP_PL_START + 1;
localparam PP_RLPF_START = PP_PL_START;
localparam PP_RLPF_LENGTH = 3;
localparam PP_RLPF_END = PP_RLPF_START + PP_RLPF_LENGTH;
localparam PP_PL_END = PP_RLPF_END;

14242
software/sys_controller/mem_init/sys_onchip_memory2_0.hex
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File diff suppressed because it is too large Load Diff

18
software/sys_controller/ossc/av_controller.c
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@ -106,6 +106,7 @@ const pll_config_t pll_configs[] = { {{0x0d806000, 0x00402010, 0x08800020, 0x000
{{0x0d806000, 0x00441c07, 0x02800020, 0x00080002, 0x00000000}}, // 3x (~20-40MHz)
{{0x0d806000, 0x00402004, 0x02800020, 0x00080002, 0x00000000}}, // 4x (~20-40MHz)
{{0x0d806000, 0x00441c05, 0x01800020, 0x00080002, 0x00000000}}, // 5x (~20-40MHz)
{{0x0d806000, 0x00301802, 0x01800020, 0x00080002, 0x00000000}}, // 6x (~20-40MHz)
{{0x0e406000, 0x00281407, 0x02800020, 0x00080002, 0x00000000}} }; // 2x (~75MHz)
volatile sc_regs *sc = (volatile sc_regs*)SC_CONFIG_0_BASE;
@ -181,7 +182,7 @@ inline void TX_enable(tx_mode_t mode)
EnableVideoOutput(cm.hdmitx_pclk_level ? PCLK_HIGH : PCLK_MEDIUM, COLOR_RGB444, (mode == TX_HDMI_YCBCR444) ? COLOR_YUV444 : COLOR_RGB444, (mode != TX_DVI));
if (mode != TX_DVI) {
HDMITX_SetAVIInfoFrame(vmode_out.vic, (mode == TX_HDMI_RGB) ? F_MODE_RGB444 : F_MODE_YUV444, 0, 0, tc.hdmi_itc, cm.hdmitx_pixr_ifr);
HDMITX_SetAVIInfoFrame(vmode_out.vic, (mode == TX_HDMI_RGB) ? F_MODE_RGB444 : F_MODE_YUV444, 0, 0, tc.hdmi_itc, vm_conf.hdmitx_pixr_ifr);
cm.cc.hdmi_itc = tc.hdmi_itc;
}
@ -553,7 +554,6 @@ void program_mode()
alt_u32 h_hz, h_synclen_px, pclk_i_hz, dotclk_hz, pll_h_total;
memset(&vmode_in, 0, sizeof(mode_data_t));
cm.tx_pixelrep = cm.hdmitx_pixr_ifr = 0;
vmode_in.timings.v_hz_x100 = (100*27000000UL)/cm.pcnt_frame;
h_hz = (100*27000000UL)/((100*cm.pcnt_frame*(1+!cm.progressive))/cm.totlines);
@ -602,7 +602,7 @@ void program_mode()
// Tweak infoframe pixel repetition indicator if passing thru horizontally multiplied mode
if ((vm_conf.y_rpt == 0) && (vm_conf.h_skip > 0))
cm.hdmitx_pixr_ifr = vm_conf.h_skip;
vm_conf.hdmitx_pixr_ifr = vm_conf.h_skip;
dotclk_hz = estimate_dotclk(&vmode_in, h_hz);
cm.pclk_o_hz = calculate_pclk(pclk_i_hz, &vmode_out, &vm_conf);
@ -640,7 +640,7 @@ void program_mode()
if (vm_conf.si_pclk_mult > 1) {
if ((vm_conf.si_pclk_mult == 2) && (pclk_i_hz > 50000000UL))
pll_reconfigure(5);
pll_reconfigure(6);
else
pll_reconfigure(vm_conf.si_pclk_mult-1);
sys_ctrl &= ~PLL_BYPASS;
@ -649,11 +649,11 @@ void program_mode()
}
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, sys_ctrl);
update_osd_size(&vmode_out);
update_osd_size(&vmode_out, &vm_conf);
update_sc_config(&vmode_in, &vmode_out, &vm_conf, &cm.cc);
TX_SetPixelRepetition(cm.tx_pixelrep, ((cm.cc.tx_mode!=TX_DVI) && (cm.tx_pixelrep == cm.hdmitx_pixr_ifr)) ? 1 : 0);
TX_SetPixelRepetition(vm_conf.tx_pixelrep, ((cm.cc.tx_mode!=TX_DVI) && (vm_conf.tx_pixelrep == vm_conf.hdmitx_pixr_ifr)) ? 1 : 0);
if (cm.pclk_o_hz > 85000000)
hdmitx_pclk_level = 1;
@ -662,14 +662,14 @@ void program_mode()
else
hdmitx_pclk_level = cm.hdmitx_pclk_level;
printf("PCLK level: %u, PR: %u, IPR: %u, ITC: %u\n", hdmitx_pclk_level, cm.tx_pixelrep, cm.hdmitx_pixr_ifr, cm.cc.hdmi_itc);
printf("PCLK level: %u, PR: %u, IPR: %u, ITC: %u\n", hdmitx_pclk_level, vm_conf.tx_pixelrep, vm_conf.hdmitx_pixr_ifr, cm.cc.hdmi_itc);
// Full TX initialization increases mode switch delay, use only when necessary
if (cm.cc.full_tx_setup || (cm.hdmitx_pclk_level != hdmitx_pclk_level)) {
cm.hdmitx_pclk_level = hdmitx_pclk_level;
TX_enable(cm.cc.tx_mode);
} else if (cm.cc.tx_mode!=TX_DVI) {
HDMITX_SetAVIInfoFrame(vmode_out.vic, (cm.cc.tx_mode == TX_HDMI_RGB) ? F_MODE_RGB444 : F_MODE_YUV444, 0, 0, cm.cc.hdmi_itc, cm.hdmitx_pixr_ifr);
HDMITX_SetAVIInfoFrame(vmode_out.vic, (cm.cc.tx_mode == TX_HDMI_RGB) ? F_MODE_RGB444 : F_MODE_YUV444, 0, 0, cm.cc.hdmi_itc, vm_conf.hdmitx_pixr_ifr);
#ifdef ENABLE_AUDIO
#ifdef MANUAL_CTS
SetupAudio(cm.cc.tx_mode);
@ -1119,7 +1119,7 @@ int main()
if ((tc.tx_mode != TX_DVI) && (tc.hdmi_itc != cm.cc.hdmi_itc)) {
//EnableAVIInfoFrame(FALSE, NULL);
printf("setting ITC to %d\n", tc.hdmi_itc);
HDMITX_SetAVIInfoFrame(vmode_out.vic, (tc.tx_mode == TX_HDMI_RGB) ? F_MODE_RGB444 : F_MODE_YUV444, 0, 0, tc.hdmi_itc, cm.hdmitx_pixr_ifr);
HDMITX_SetAVIInfoFrame(vmode_out.vic, (tc.tx_mode == TX_HDMI_RGB) ? F_MODE_RGB444 : F_MODE_YUV444, 0, 0, tc.hdmi_itc, vm_conf.hdmitx_pixr_ifr);
cm.cc.hdmi_itc = tc.hdmi_itc;
}
if (tc.av3_alt_rgb != cm.cc.av3_alt_rgb) {

2
software/sys_controller/ossc/av_controller.h
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@ -82,8 +82,6 @@ typedef struct {
alt_u8 progressive;
alt_8 id;
alt_u8 sync_active;
alt_u8 tx_pixelrep;
alt_u8 hdmitx_pixr_ifr;
alt_u8 hdmitx_pclk_level;
alt_u32 pclk_o_hz;
avinput_t avinput;

1
software/sys_controller/ossc/avconfig.h
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@ -93,6 +93,7 @@ typedef struct {
alt_u8 l3_mode;
alt_u8 l4_mode;
alt_u8 l5_mode;
alt_u8 l6_mode;
alt_u8 l5_fmt;
alt_u8 s480p_mode;
alt_u8 s400p_mode;

4
software/sys_controller/ossc/firmware.h
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@ -24,10 +24,10 @@
#include "sysconfig.h"
#define FW_VER_MAJOR 1
#define FW_VER_MINOR 04
#define FW_VER_MINOR 05
#define PROFILE_VER_MAJOR 1
#define PROFILE_VER_MINOR 03
#define PROFILE_VER_MINOR 05
#define INITCFG_VER_MAJOR 1
#define INITCFG_VER_MINOR 00

21
software/sys_controller/ossc/menu.c
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@ -56,9 +56,9 @@ static const char *s400p_mode_desc[] = { "VGA 640x400@70", "VGA 720x400@70" };
static const char *sync_lpf_desc[] = { LNG("2.5MHz (max)","2.5MHz (ｻｲﾀﾞｲ)"), LNG("10MHz (med)","10MHz (ﾁｭｳｲ)"), LNG("33MHz (min)","33MHz (ｻｲｼｮｳ)"), LNG("Off","ｵﾌ") };
static const char *stc_lpf_desc[] = { "4.8MHz (HDTV/PC)", "0.5MHz (SDTV)", "1.7MHz (EDTV)" };
static const char *l3_mode_desc[] = { LNG("Generic 16:9","ｼﾞｪﾈﾘｯｸ 16:9"), LNG("Generic 4:3","ｼﾞｪﾈﾘｯｸ 4:3"), LNG("512x240 optim.","512x240 ｻｲﾃｷｶ."), LNG("384x240 optim.","384x240 ｻｲﾃｷｶ."), LNG("320x240 optim.","320x240 ｻｲﾃｷｶ."), LNG("256x240 optim.","256x240 ｻｲﾃｷｶ.") };
static const char *l2l4l5_mode_desc[] = { LNG("Generic 4:3","ｼﾞｪﾈﾘｯｸ 4:3"), LNG("512x240 optim.","512x240 ｻｲﾃｷｶ."), LNG("384x240 optim.","384x240 ｻｲﾃｷｶ."), LNG("320x240 optim.","320x240 ｻｲﾃｷｶ."), LNG("256x240 optim.","256x240 ｻｲﾃｷｶ.") };
static const char *l2l4l5l6_mode_desc[] = { LNG("Generic 4:3","ｼﾞｪﾈﾘｯｸ 4:3"), LNG("512x240 optim.","512x240 ｻｲﾃｷｶ."), LNG("384x240 optim.","384x240 ｻｲﾃｷｶ."), LNG("320x240 optim.","320x240 ｻｲﾃｷｶ."), LNG("256x240 optim.","256x240 ｻｲﾃｷｶ.") };
static const char *l5_fmt_desc[] = { "1920x1080", "1600x1200", "1920x1200" };
static const char *pm_240p_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x", "Line3x", "Line4x", "Line5x" };
static const char *pm_240p_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x", "Line3x", "Line4x", "Line5x", "Line6x" };
static const char *pm_480i_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x (bob)", "Line3x (laced)", "Line4x (bob)" };
static const char *pm_384p_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x", "Line3x Generic", "Line2x 240x360", "Line3x 240x360" };
static const char *pm_480p_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x" };
@ -176,10 +176,11 @@ MENU(menu_output, P99_PROTECT({ \
{ LNG("480i/576i proc","480i/576iｼｮﾘ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_480i, OPT_WRAP, SETTING_ITEM(pm_480i_desc) } } },
{ LNG("480p/576p proc","480p/576pｼｮﾘ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_480p, OPT_WRAP, SETTING_ITEM(pm_480p_desc) } } },
{ LNG("960i/1080i proc","960i/1080iｼｮﾘ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_1080i, OPT_WRAP, SETTING_ITEM(pm_1080i_desc) } } },
{ LNG("Line2x mode","Line2xﾓｰﾄﾞ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.l2_mode, OPT_WRAP, SETTING_ITEM(l2l4l5_mode_desc) } } },
{ LNG("Line2x mode","Line2xﾓｰﾄﾞ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.l2_mode, OPT_WRAP, SETTING_ITEM(l2l4l5l6_mode_desc) } } },
{ LNG("Line3x mode","Line3xﾓｰﾄﾞ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.l3_mode, OPT_WRAP, SETTING_ITEM(l3_mode_desc) } } },
{ LNG("Line4x mode","Line4xﾓｰﾄﾞ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.l4_mode, OPT_WRAP, SETTING_ITEM(l2l4l5_mode_desc) } } },
{ LNG("Line5x mode","Line5xﾓｰﾄﾞ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.l5_mode, OPT_WRAP, SETTING_ITEM(l2l4l5_mode_desc) } } },
{ LNG("Line4x mode","Line4xﾓｰﾄﾞ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.l4_mode, OPT_WRAP, SETTING_ITEM(l2l4l5l6_mode_desc) } } },
{ LNG("Line5x mode","Line5xﾓｰﾄﾞ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.l5_mode, OPT_WRAP, SETTING_ITEM(l2l4l5l6_mode_desc) } } },
{ LNG("Line6x mode","Line6xﾓｰﾄﾞ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.l6_mode, OPT_WRAP, SETTING_ITEM(l2l4l5l6_mode_desc) } } },
{ LNG("Line5x format","Line5xｹｲｼｷ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.l5_fmt, OPT_WRAP, SETTING_ITEM(l5_fmt_desc) } } },
{ LNG("256x240 aspect","256x240ｱｽﾍﾟｸﾄ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.ar_256col, OPT_WRAP, SETTING_ITEM(ar_256col_desc) } } },
{ LNG("TX mode","TXﾓｰﾄﾞ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.tx_mode, OPT_WRAP, SETTING_ITEM(tx_mode_desc) } } },
@ -470,7 +471,7 @@ void display_menu(alt_u8 forcedisp)
ui_disp_menu(0);
}
void update_osd_size(mode_data_t *vm_out) {
void update_osd_size(mode_data_t *vm_out, vm_proc_config_t *vm_conf) {
uint8_t osd_size = vm_out->timings.v_active / 700;
uint8_t par = (((100*vm_out->timings.h_active*vm_out->ar.v)/((vm_out->timings.v_active<<vm_out->timings.interlaced)*vm_out->ar.h))+50)/100;
uint8_t par_log2 = 0;
@ -483,10 +484,10 @@ void update_osd_size(mode_data_t *vm_out) {
osd->osd_config.x_size = osd_size + vm_out->timings.interlaced + par_log2;
osd->osd_config.y_size = osd_size;
if (cm.hdmitx_pixr_ifr)
osd->osd_config.x_size += (cm.hdmitx_pixr_ifr+1)/2;
if (cm.tx_pixelrep)
osd->osd_config.x_size -= (cm.tx_pixelrep+1)/2;
if (vm_conf->hdmitx_pixr_ifr)
osd->osd_config.x_size += (vm_conf->hdmitx_pixr_ifr+1)/2;
if (vm_conf->tx_pixelrep)
osd->osd_config.x_size -= (vm_conf->tx_pixelrep+1)/2;
}
static void vm_select() {

2
software/sys_controller/ossc/menu.h
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@ -127,7 +127,7 @@ void init_menu();
void render_osd_page();
void display_menu(alt_u8 forcedisp);
void sampler_phase_disp(alt_u8 v);
void update_osd_size(mode_data_t *vm_out);
void update_osd_size(mode_data_t *vm_out, vm_proc_config_t *vm_conf);
static void vm_select();
static void vm_tweak(alt_u16 *v);

38
software/sys_controller/ossc/video_modes.c
View File

@ -126,6 +126,8 @@ uint32_t calculate_pclk(uint32_t src_clk_hz, mode_data_t *vm_out, vm_proc_config
}
}
pclk_hz *= vm_conf->tx_pixelrep+1;
return pclk_hz;
}
@ -133,7 +135,7 @@ int get_pure_lm_mode(avconfig_t *cc, mode_data_t *vm_in, mode_data_t *vm_out, vm
{
int i, diff_lines, diff_v_hz_x100, mindiff_id=0, mindiff_lines=1000, mindiff_v_hz_x100=10000;
mode_data_t *mode_preset;
mode_flags valid_lm[] = { MODE_PT, (MODE_L2 | (MODE_L2<<cc->l2_mode)), (MODE_L3_GEN_16_9<<cc->l3_mode), (MODE_L4_GEN_4_3<<cc->l4_mode), (MODE_L5_GEN_4_3<<cc->l5_mode) };
mode_flags valid_lm[] = { MODE_PT, (MODE_L2 | (MODE_L2<<cc->l2_mode)), (MODE_L3_GEN_16_9<<cc->l3_mode), (MODE_L4_GEN_4_3<<cc->l4_mode), (MODE_L5_GEN_4_3<<cc->l5_mode), (MODE_L6_GEN_4_3<<cc->l6_mode) };
mode_flags target_lm, mindiff_lm;
uint8_t pt_only = 0;
uint8_t upsample2x = cc->upsample2x;
@ -401,6 +403,9 @@ int get_pure_lm_mode(avconfig_t *cc, mode_data_t *vm_in, mode_data_t *vm_out, vm
vm_conf->y_rpt = 4;
vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
vm_conf->si_pclk_mult = VM_OUT_PCLKMULT;
// Force TX pixel-repeat
if (mode_preset->group == GROUP_288P)
vm_conf->tx_pixelrep = 1;
break;
case MODE_L5_512_COL:
vm_conf->y_rpt = 4;
@ -427,6 +432,35 @@ int get_pure_lm_mode(avconfig_t *cc, mode_data_t *vm_in, mode_data_t *vm_out, vm
vm_conf->si_pclk_mult = VM_OUT_PCLKMULT;
vm_conf->x_rpt -= cc->ar_256col;
break;
case MODE_L6_GEN_4_3:
vm_conf->y_rpt = 5;
vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
vm_conf->si_pclk_mult = VM_OUT_PCLKMULT;
vm_conf->tx_pixelrep = 1;
break;
case MODE_L6_512_COL:
vm_conf->y_rpt = 5;
vm_conf->x_rpt = vm_conf->h_skip = 1;
vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
vm_conf->si_pclk_mult = VM_OUT_PCLKMULT;
vm_conf->tx_pixelrep = 1;
break;
case MODE_L6_384_COL:
case MODE_L6_320_COL:
vm_conf->y_rpt = 5;
vm_conf->x_rpt = vm_conf->h_skip = 2;
vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
vm_conf->si_pclk_mult = VM_OUT_PCLKMULT;
vm_conf->tx_pixelrep = 1;
break;
case MODE_L6_256_COL:
vm_conf->y_rpt = 5;
vm_conf->x_rpt = vm_conf->h_skip = 3;
vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
vm_conf->si_pclk_mult = VM_OUT_PCLKMULT;
vm_conf->x_rpt = cc->ar_256col ? 2 : 3;
vm_conf->tx_pixelrep = 1;
break;
default:
printf("WARNING: invalid mindiff_lm\n");
return -1;
@ -445,7 +479,7 @@ int get_pure_lm_mode(avconfig_t *cc, mode_data_t *vm_in, mode_data_t *vm_out, vm
vm_conf->y_offset = ((vm_out->timings.v_active-vm_conf->y_size)/2);
// Line5x format
if (vm_conf->y_rpt == 4) {
if ((vm_conf->y_rpt == 4) && !((mindiff_lm == MODE_L5_GEN_4_3) && (mode_preset->group == GROUP_288P))) {
// adjust output width to 1920
if (cc->l5_fmt != 1) {
vm_conf->x_offset = (1920-vm_conf->x_size)/2;

11
software/sys_controller/ossc/video_modes.h
View File

@ -42,7 +42,7 @@
#define V_BPORCH_MIN 0
#define V_BPORCH_MAX 511
#define V_ACTIVE_MIN 160
#define V_ACTIVE_MAX 1440
#define V_ACTIVE_MAX 1728
typedef enum {
FORMAT_RGBS = 0,
@ -100,10 +100,15 @@ typedef enum {
MODE_L5_384_COL = (1<<23),
MODE_L5_320_COL = (1<<24),
MODE_L5_256_COL = (1<<25),
MODE_L6_GEN_4_3 = (1<<26),
MODE_L6_512_COL = (1<<27),
MODE_L6_384_COL = (1<<28),
MODE_L6_320_COL = (1<<29),
MODE_L6_256_COL = (1<<30),
} mode_flags;
typedef enum {
VMODE_480p = 24,
VMODE_480p = 23,
} vmode_t;
typedef struct {
@ -163,6 +168,8 @@ typedef struct {
uint8_t x_start_lb;
int8_t y_start_lb;
uint8_t framelock;
uint8_t tx_pixelrep;
uint8_t hdmitx_pixr_ifr;
// for generation from 27MHz clock
int8_t si_pclk_mult;
} vm_proc_config_t;

83
software/sys_controller/ossc/video_modes_list.c
View File

@ -23,62 +23,61 @@ static
#endif
const mode_data_t video_modes_plm_default[] = {
/* 240p modes */
{ "1600x240", HDMI_Unknown, {1600, 240, 6000, 2046, 0, 262, 202, 15, 150, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_240P, (MODE_L5_GEN_4_3), },
{ "1280x240", HDMI_Unknown, {1280, 240, 6000, 1560, 0, 262, 170, 15, 72, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_240P, (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3), },
{ "960x240", HDMI_Unknown, { 960, 240, 6000, 1170, 0, 262, 128, 15, 54, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_240P, (MODE_L3_GEN_4_3), },
{ "512x240", HDMI_Unknown, { 512, 240, 6000, 682, 0, 262, 77, 14, 50, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_240P, (MODE_L2_512_COL | MODE_L3_512_COL | MODE_L4_512_COL | MODE_L5_512_COL), },
{ "384x240", HDMI_Unknown, { 384, 240, 6000, 512, 0, 262, 59, 14, 37, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_240P, (MODE_L2_384_COL | MODE_L3_384_COL | MODE_L4_384_COL | MODE_L5_384_COL), },
{ "320x240", HDMI_Unknown, { 320, 240, 6000, 426, 0, 262, 49, 14, 31, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_240P, (MODE_L2_320_COL | MODE_L3_320_COL | MODE_L4_320_COL | MODE_L5_320_COL), },
{ "256x240", HDMI_Unknown, { 256, 240, 6000, 341, 0, 262, 39, 14, 25, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_240P, (MODE_L2_256_COL | MODE_L3_256_COL | MODE_L4_256_COL | MODE_L5_256_COL), },
{ "240p", HDMI_240p60, { 720, 240, 6005, 858, 0, 262, 57, 15, 62, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_240P, (MODE_PT | MODE_L2), },
{ "1600x240", HDMI_Unknown, {1600, 240, 6000, 2046, 0, 262, 202, 15, 150, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_240P, (MODE_L5_GEN_4_3), },
{ "1280x240", HDMI_Unknown, {1280, 240, 6000, 1560, 0, 262, 170, 15, 72, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_240P, (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3), },
{ "960x240", HDMI_Unknown, { 960, 240, 6000, 1170, 0, 262, 128, 15, 54, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_240P, (MODE_L3_GEN_4_3 | MODE_L6_GEN_4_3), },
{ "512x240", HDMI_Unknown, { 512, 240, 6000, 682, 0, 262, 77, 14, 50, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_240P, (MODE_L2_512_COL | MODE_L3_512_COL | MODE_L4_512_COL | MODE_L5_512_COL | MODE_L6_512_COL), },
{ "384x240", HDMI_Unknown, { 384, 240, 6000, 512, 0, 262, 59, 14, 37, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_240P, (MODE_L2_384_COL | MODE_L3_384_COL | MODE_L4_384_COL | MODE_L5_384_COL | MODE_L6_384_COL), },
{ "320x240", HDMI_Unknown, { 320, 240, 6000, 426, 0, 262, 49, 14, 31, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_240P, (MODE_L2_320_COL | MODE_L3_320_COL | MODE_L4_320_COL | MODE_L5_320_COL | MODE_L6_320_COL), },
{ "256x240", HDMI_Unknown, { 256, 240, 6000, 341, 0, 262, 39, 14, 25, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_240P, (MODE_L2_256_COL | MODE_L3_256_COL | MODE_L4_256_COL | MODE_L5_256_COL | MODE_L6_256_COL), },
{ "240p", HDMI_240p60, { 720, 240, 6005, 858, 0, 262, 57, 15, 62, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_240P, (MODE_PT | MODE_L2), },
/* 288p modes */
{ "1600x240L", HDMI_Unknown, {1600, 240, 5000, 2046, 0, 312, 202, 43, 150, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_288P, (MODE_L5_GEN_4_3), },
{ "1280x288", HDMI_Unknown, {1280, 288, 5000, 1560, 0, 312, 170, 19, 72, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_288P, (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3), },
{ "960x288", HDMI_Unknown, { 960, 288, 5000, 1170, 0, 312, 128, 19, 54, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_288P, (MODE_L3_GEN_4_3), },
{ "512x240LB", HDMI_Unknown, { 512, 240, 5000, 682, 0, 312, 77, 41, 50, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_288P, (MODE_L2_512_COL | MODE_L3_512_COL | MODE_L4_512_COL | MODE_L5_512_COL), },
{ "384x240LB", HDMI_Unknown, { 384, 240, 5000, 512, 0, 312, 59, 41, 37, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_288P, (MODE_L2_384_COL | MODE_L3_384_COL | MODE_L4_384_COL | MODE_L5_384_COL), },
{ "320x240LB", HDMI_Unknown, { 320, 240, 5000, 426, 0, 312, 49, 41, 31, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_288P, (MODE_L2_320_COL | MODE_L3_320_COL | MODE_L4_320_COL | MODE_L5_320_COL), },
{ "256x240LB", HDMI_Unknown, { 256, 240, 5000, 341, 0, 312, 39, 41, 25, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_288P, (MODE_L2_256_COL | MODE_L3_256_COL | MODE_L4_256_COL | MODE_L5_256_COL), },
{ "288p", HDMI_288p50, { 720, 288, 5008, 864, 0, 312, 69, 19, 63, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_288P, (MODE_PT | MODE_L2), },
{ "1280x288", HDMI_Unknown, {1280, 288, 5000, 1560, 0, 312, 170, 19, 72, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_288P, (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_L6_GEN_4_3), },
{ "960x288", HDMI_Unknown, { 960, 288, 5000, 1170, 0, 312, 128, 19, 54, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_288P, (MODE_L3_GEN_4_3 | MODE_L5_GEN_4_3), },
{ "512x240LB", HDMI_Unknown, { 512, 240, 5000, 682, 0, 312, 77, 41, 50, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_288P, (MODE_L2_512_COL | MODE_L3_512_COL | MODE_L4_512_COL | MODE_L5_512_COL | MODE_L6_512_COL), },
{ "384x240LB", HDMI_Unknown, { 384, 240, 5000, 512, 0, 312, 59, 41, 37, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_288P, (MODE_L2_384_COL | MODE_L3_384_COL | MODE_L4_384_COL | MODE_L5_384_COL | MODE_L6_384_COL), },
{ "320x240LB", HDMI_Unknown, { 320, 240, 5000, 426, 0, 312, 49, 41, 31, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_288P, (MODE_L2_320_COL | MODE_L3_320_COL | MODE_L4_320_COL | MODE_L5_320_COL | MODE_L6_320_COL), },
{ "256x240LB", HDMI_Unknown, { 256, 240, 5000, 341, 0, 312, 39, 41, 25, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_288P, (MODE_L2_256_COL | MODE_L3_256_COL | MODE_L4_256_COL | MODE_L5_256_COL | MODE_L6_256_COL), },
{ "288p", HDMI_288p50, { 720, 288, 5008, 864, 0, 312, 69, 19, 63, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_288P, (MODE_PT | MODE_L2), },
/* 360p: GBI */
{ "480x360", HDMI_Unknown, { 480, 360, 6000, 600, 0, 375, 63, 10, 38, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_EDTV, GROUP_384P, (MODE_PT | MODE_L2), },
{ "240x360", HDMI_Unknown, { 256, 360, 6000, 300, 0, 375, 24, 10, 18, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_EDTV, GROUP_384P, (MODE_L2_240x360 | MODE_L3_240x360), },
{ "480x360", HDMI_Unknown, { 480, 360, 6000, 600, 0, 375, 63, 10, 38, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_EDTV, GROUP_384P, (MODE_PT | MODE_L2), },
{ "240x360", HDMI_Unknown, { 256, 360, 6000, 300, 0, 375, 24, 10, 18, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_EDTV, GROUP_384P, (MODE_L2_240x360 | MODE_L3_240x360), },
/* 384p: Sega Model 2 */
{ "384p", HDMI_Unknown, { 496, 384, 5500, 640, 0, 423, 50, 29, 62, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_EDTV, GROUP_384P, (MODE_PT | MODE_L2), },
{ "384p", HDMI_Unknown, { 496, 384, 5500, 640, 0, 423, 50, 29, 62, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_EDTV, GROUP_384P, (MODE_PT | MODE_L2), },
/* 400p line3x */
{ "1600x400", HDMI_Unknown, {1600, 400, 7000, 2000, 0, 449, 120, 34, 240, 2, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_PC, GROUP_384P, (MODE_L3_GEN_16_9), },
{ "1600x400", HDMI_Unknown, {1600, 400, 7000, 2000, 0, 449, 120, 34, 240, 2, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_PC, GROUP_384P, (MODE_L3_GEN_16_9), },
/* 720x400@70Hz, VGA Mode 3+/7+ */
{ "720x400_70", HDMI_Unknown, { 720, 400, 7000, 900, 0, 449, 64, 34, 96, 2, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_PC, GROUP_384P, (MODE_PT | MODE_L2), },
{ "720x400_70", HDMI_Unknown, { 720, 400, 7000, 900, 0, 449, 64, 34, 96, 2, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_PC, GROUP_384P, (MODE_PT | MODE_L2), },
/* 640x400@70Hz, VGA Mode 13h */
{ "640x400_70", HDMI_Unknown, { 640, 400, 7000, 800, 0, 449, 48, 34, 96, 2, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_PC, GROUP_384P, (MODE_PT | MODE_L2), },
{ "640x400_70", HDMI_Unknown, { 640, 400, 7000, 800, 0, 449, 48, 34, 96, 2, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_PC, GROUP_384P, (MODE_PT | MODE_L2), },
/* 384p: X68k @ 24kHz */
{ "640x384", HDMI_Unknown, { 640, 384, 5500, 800, 0, 492, 48, 63, 96, 2, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_PC, GROUP_384P, (MODE_PT | MODE_L2), },
{ "640x384", HDMI_Unknown, { 640, 384, 5500, 800, 0, 492, 48, 63, 96, 2, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_PC, GROUP_384P, (MODE_PT | MODE_L2), },
/* ~525-line modes */
{ "480i", HDMI_480i60, { 720, 240, 5994, 858, 0, 525, 57, 15, 62, 3, 1}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_480I, (MODE_PT | MODE_L2 | MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3), },
{ "480p", HDMI_480p60, { 720, 480, 5994, 858, 0, 525, 60, 30, 62, 6, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_EDTV, GROUP_480P, (MODE_PT | MODE_L2), },
{ "640x480_60", HDMI_640x480p60, { 640, 480, 6000, 800, 0, 525, 48, 33, 96, 2, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_PC, GROUP_480P, (MODE_PT | MODE_L2), },
{ "480i", HDMI_480i60, { 720, 240, 5994, 858, 0, 525, 57, 15, 62, 3, 1}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_480I, (MODE_PT | MODE_L2 | MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3), },
{ "480p", HDMI_480p60, { 720, 480, 5994, 858, 0, 525, 60, 30, 62, 6, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_EDTV, GROUP_480P, (MODE_PT | MODE_L2), },
{ "640x480_60", HDMI_640x480p60, { 640, 480, 6000, 800, 0, 525, 48, 33, 96, 2, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_PC, GROUP_480P, (MODE_PT | MODE_L2), },
/* 480p PSP in-game */ \
{ "480x272", HDMI_480p60_16x9, { 480, 272, 6000, 858, 0, 525, 177,134, 62, 6, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_EDTV, GROUP_480P, (MODE_PT | MODE_L2) }, \
{ "480x272", HDMI_480p60_16x9, { 480, 272, 6000, 858, 0, 525, 177,134, 62, 6, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_EDTV, GROUP_480P, (MODE_PT | MODE_L2) }, \
/* X68k @ 31kHz */
{ "640x512", HDMI_Unknown, { 640, 512, 6000, 800, 0, 568, 48, 34, 96, 6, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_PC, GROUP_480P, (MODE_PT | MODE_L2), },
{ "640x512", HDMI_Unknown, { 640, 512, 6000, 800, 0, 568, 48, 34, 96, 6, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_PC, GROUP_480P, (MODE_PT | MODE_L2), },
/* ~625-line modes */
{ "576i", HDMI_576i50, { 720, 288, 5000, 864, 0, 625, 69, 19, 63, 3, 1}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_576I, (MODE_PT | MODE_L2 | MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3), },
{ "576p", HDMI_576p50, { 720, 576, 5000, 864, 0, 625, 68, 39, 64, 5, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_EDTV, GROUP_576P, (MODE_PT | MODE_L2), },
{ "800x600_60", HDMI_Unknown, { 800, 600, 6000, 1056, 0, 628, 88, 23, 128, 4, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_PC, GROUP_NONE, MODE_PT, },
{ "576i", HDMI_576i50, { 720, 288, 5000, 864, 0, 625, 69, 19, 63, 3, 1}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_576I, (MODE_PT | MODE_L2 | MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3), },
{ "576p", HDMI_576p50, { 720, 576, 5000, 864, 0, 625, 68, 39, 64, 5, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_EDTV, GROUP_576P, (MODE_PT | MODE_L2), },
{ "800x600_60", HDMI_Unknown, { 800, 600, 6000, 1056, 0, 628, 88, 23, 128, 4, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_PC, GROUP_NONE, MODE_PT, },
/* CEA 720p modes */
{ "720p_50", HDMI_720p50, {1280, 720, 5000, 1980, 0, 750, 220, 20, 40, 5, 0}, DEF_PHASE, {{ 0, 0}}, (VIDEO_HDTV | VIDEO_PC), GROUP_720P, MODE_PT, },
{ "720p_60", HDMI_720p60, {1280, 720, 6000, 1650, 0, 750, 220, 20, 40, 5, 0}, DEF_PHASE, {{ 0, 0}}, (VIDEO_HDTV | VIDEO_PC), GROUP_720P, MODE_PT, },
{ "720p_50", HDMI_720p50, {1280, 720, 5000, 1980, 0, 750, 220, 20, 40, 5, 0}, DEF_PHASE, {{ 0, 0}}, (VIDEO_HDTV | VIDEO_PC), GROUP_720P, MODE_PT, },
{ "720p_60", HDMI_720p60, {1280, 720, 6000, 1650, 0, 750, 220, 20, 40, 5, 0}, DEF_PHASE, {{ 0, 0}}, (VIDEO_HDTV | VIDEO_PC), GROUP_720P, MODE_PT, },
/* VESA XGA,1280x960 and SXGA modes */
{ "1024x768", HDMI_Unknown, {1024, 768, 6000, 1344, 0, 806, 160, 29, 136, 6, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_PC, GROUP_NONE, MODE_PT, },
{ "1280x960", HDMI_Unknown, {1280, 960, 6000, 1800, 0, 1000, 312, 36, 112, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_PC, GROUP_NONE, MODE_PT, },
{ "1280x1024", HDMI_Unknown, {1280, 1024, 6000, 1688, 0, 1066, 248, 38, 112, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_PC, GROUP_NONE, MODE_PT, },
{ "1024x768", HDMI_Unknown, {1024, 768, 6000, 1344, 0, 806, 160, 29, 136, 6, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_PC, GROUP_NONE, MODE_PT, },
{ "1280x960", HDMI_Unknown, {1280, 960, 6000, 1800, 0, 1000, 312, 36, 112, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_PC, GROUP_NONE, MODE_PT, },
{ "1280x1024", HDMI_Unknown, {1280, 1024, 6000, 1688, 0, 1066, 248, 38, 112, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_PC, GROUP_NONE, MODE_PT, },
/* PS2 GSM 960i mode */
{ "640x960i", HDMI_Unknown, { 640, 480, 6000, 800, 0, 1050, 48, 33, 96, 2, 1}, DEF_PHASE, {{ 0, 0}}, VIDEO_EDTV, GROUP_1080I, (MODE_PT | MODE_L2), },
{ "640x960i", HDMI_Unknown, { 640, 480, 6000, 800, 0, 1050, 48, 33, 96, 2, 1}, DEF_PHASE, {{ 0, 0}}, VIDEO_EDTV, GROUP_1080I, (MODE_PT | MODE_L2), },
/* CEA 1080i/p modes */
{ "1080i_50", HDMI_1080i50, {1920, 540, 5000, 2640, 0, 1125, 148, 15, 44, 5, 1}, DEF_PHASE, {{ 0, 0}}, (VIDEO_HDTV | VIDEO_PC), GROUP_1080I, (MODE_PT | MODE_L2), },
{ "1080i_60", HDMI_1080i60, {1920, 540, 6000, 2200, 0, 1125, 148, 15, 44, 5, 1}, DEF_PHASE, {{ 0, 0}}, (VIDEO_HDTV | VIDEO_PC), GROUP_1080I, (MODE_PT | MODE_L2), },
{ "1080p_50", HDMI_1080p50, {1920, 1080, 5000, 2640, 0, 1125, 148, 36, 44, 5, 0}, DEF_PHASE, {{ 0, 0}}, (VIDEO_HDTV | VIDEO_PC), GROUP_1080P, MODE_PT, },
{ "1080p_60", HDMI_1080p60, {1920, 1080, 6000, 2200, 0, 1125, 148, 36, 44, 5, 0}, DEF_PHASE, {{ 0, 0}}, (VIDEO_HDTV | VIDEO_PC), GROUP_1080P, MODE_PT, },
{ "1080i_50", HDMI_1080i50, {1920, 540, 5000, 2640, 0, 1125, 148, 15, 44, 5, 1}, DEF_PHASE, {{ 0, 0}}, (VIDEO_HDTV | VIDEO_PC), GROUP_1080I, (MODE_PT | MODE_L2), },
{ "1080i_60", HDMI_1080i60, {1920, 540, 6000, 2200, 0, 1125, 148, 15, 44, 5, 1}, DEF_PHASE, {{ 0, 0}}, (VIDEO_HDTV | VIDEO_PC), GROUP_1080I, (MODE_PT | MODE_L2), },
{ "1080p_50", HDMI_1080p50, {1920, 1080, 5000, 2640, 0, 1125, 148, 36, 44, 5, 0}, DEF_PHASE, {{ 0, 0}}, (VIDEO_HDTV | VIDEO_PC), GROUP_1080P, MODE_PT, },
{ "1080p_60", HDMI_1080p60, {1920, 1080, 6000, 2200, 0, 1125, 148, 36, 44, 5, 0}, DEF_PHASE, {{ 0, 0}}, (VIDEO_HDTV | VIDEO_PC), GROUP_1080P, MODE_PT, },
/* VESA UXGA mode */
{ "1600x1200", HDMI_Unknown, {1600, 1200, 6000, 2160, 0, 1250, 304, 46, 192, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_PC, GROUP_NONE, MODE_PT, },
{ "1600x1200", HDMI_Unknown, {1600, 1200, 6000, 2160, 0, 1250, 304, 46, 192, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_PC, GROUP_NONE, MODE_PT, },
};