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update epcq_controller_mod to epcq_controller2

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marqs 2020-11-10 19:45:52 +02:00
parent 2a24eb8dd7
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30 changed files with 9313 additions and 11637 deletions
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// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1ps / 1ps
module altera_epcq_controller #(
parameter CS_WIDTH = 1,
parameter ENABLE_4BYTE_ADDR = 1,
parameter ADDR_WIDTH = 22,
parameter ASI_WIDTH = 1,
parameter DEVICE_FAMILY = "CYCLONE V",
parameter ASMI_ADDR_WIDTH = 22,
parameter CHIP_SELS = 1
)(
input wire clk,
input wire reset_n,
// ports to access csr
input wire avl_csr_write,
input wire avl_csr_read,
input wire [2:0] avl_csr_addr,
input wire [31:0] avl_csr_wrdata,
output reg [31:0] avl_csr_rddata,
output reg avl_csr_rddata_valid,
output reg avl_csr_waitrequest,
// ports to access memory
input wire avl_mem_write,
input wire avl_mem_read,
input wire [ADDR_WIDTH-1:0] avl_mem_addr,
input wire [31:0] avl_mem_wrdata,
input wire [3:0] avl_mem_byteenable,
input wire [6:0] avl_mem_burstcount,
output wire [31:0] avl_mem_rddata,
output reg avl_mem_rddata_valid,
output reg avl_mem_waitrequest,
// interrupt signal
output reg irq,
// Disable dedicated active serial interface
input wire [ASI_WIDTH-1:0] epcq_dataout,
output reg epcq_dclk,
output reg [CS_WIDTH-1:0] epcq_scein,
output reg [ASI_WIDTH-1:0] epcq_sdoin,
output reg [ASI_WIDTH-1:0] epcq_dataoe,
// ASMI PARALLEL interface
input wire [ASI_WIDTH-1:0] ddasi_dataoe,
output reg [ASI_WIDTH-1:0] ddasi_dataout,
input wire ddasi_dclk,
input wire [CS_WIDTH-1:0] ddasi_scein,
input reg [ASI_WIDTH-1:0] ddasi_sdoin,
input wire asmi_busy,
input wire asmi_data_valid,
input wire [7:0] asmi_dataout,
output reg asmi_clkin,
output reg asmi_reset,
output reg [CS_WIDTH-1:0] asmi_sce,
output reg [ASMI_ADDR_WIDTH-1:0] asmi_addr,
output reg [7:0] asmi_datain,
output reg asmi_fast_read,
output wire asmi_rden,
output reg asmi_shift_bytes,
output reg asmi_en4b_addr,
output wire asmi_wren,
output reg asmi_write,
input wire asmi_illegal_erase,
input wire asmi_illegal_write,
input wire [7:0] asmi_rdid_out,
input wire [7:0] asmi_status_out,
input wire [7:0] asmi_epcs_id,
output reg asmi_read_rdid,
output reg asmi_read_status,
output reg asmi_read_sid,
output reg asmi_bulk_erase,
output reg asmi_sector_erase,
output reg asmi_sector_protect
);
localparam LOCAL_ADDR_WIDTH = ADDR_WIDTH+2;
localparam CSR_DATA_WIDTH = 32;
localparam LAST_ADDR_BIT = (ASMI_ADDR_WIDTH == 24) ? 15 :
(ASMI_ADDR_WIDTH == 32) ? 23 : 15;
reg [8:0] wr_burstcount_cnt, rd_burstcount_cnt;
reg [8:0] rd_mem_burstcount, wr_mem_burstcount;
wire last_wr_byte;
wire access_csr_status, access_csr_sid, access_csr_rdid, access_csr_mem_op, access_isr, access_imr, access_sce;
wire read_status_combi, read_sid_combi, read_rdid_combi, read_isr_combi, read_imr_combi, write_isr_combi, write_imr_combi, write_sce_combi;
wire bulk_erase_combi, sector_erase_combi, sector_protect_combi;
wire wren_combi, illegal_write_combi, illegal_erase_combi;
wire m_illegal_write_combi, m_illegal_erase_combi;
wire read_mem_combi, write_mem_combi;
wire data_valid_combi, pending_wr_data;
wire detect_addroffset;
wire [8:0] wfifo_data_in_0, wfifo_data_in_1, wfifo_data_in_2, wfifo_data_in_3;
wire [ADDR_WIDTH-1:0] temp_mem_addr;
reg reset_n_reg;
reg wr_mem_waitrequest, local_waitrequest;
reg illegal_write_reg, illegal_erase_reg, m_illegal_write_reg, m_illegal_erase_reg;
reg read_status_valid, read_sid_valid, read_rdid_valid, read_isr_valid, read_imr_valid;
reg read_status_en, read_sid_en, read_rdid_en;
reg wren_internal;
reg [LOCAL_ADDR_WIDTH-1:0] wr_mem_addr;
reg [7:0] rd_data_reg [4];
reg [3:0][8:0] wr_data_reg;
reg [1:0] rd_cnt;
reg [1:0] wr_cnt;
reg [3:0] wr_data_reg_full;
reg detect_addroffset_reg, asmi_busy_reg;
reg [2:0] temp_sce;
// Direct connection
assign asmi_clkin = clk;
assign asmi_reset = ~reset_n;
assign ddasi_dataout = epcq_dataout;
assign epcq_dclk = ddasi_dclk;
assign epcq_scein = ddasi_scein;
assign epcq_sdoin = ddasi_sdoin;
assign epcq_dataoe = ddasi_dataoe;
// chip select
generate if (DEVICE_FAMILY == "Arria 10") begin
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
asmi_sce <= {CS_WIDTH{1'b0}};
end
// to pack the address space this is needed
else if (write_mem_combi || read_mem_combi) begin
if (CHIP_SELS == 1 )
asmi_sce <= 3'b001;
else if (CHIP_SELS == 2 && avl_mem_addr[ADDR_WIDTH-1] == 0)
asmi_sce <= 3'b001;
else if (CHIP_SELS == 2 && avl_mem_addr[ADDR_WIDTH-1] == 1)
asmi_sce <= 3'b010;
else if (CHIP_SELS == 3 && avl_mem_addr[ADDR_WIDTH-1] == 1)
asmi_sce <= 3'b100;
else if (CHIP_SELS == 3 && avl_mem_addr[ADDR_WIDTH-1:ADDR_WIDTH-2] == 0)
asmi_sce <= 3'b001;
else if (CHIP_SELS == 3 && avl_mem_addr[ADDR_WIDTH-1:ADDR_WIDTH-2] == 1)
asmi_sce <= 3'b010;
else
asmi_sce <= {CS_WIDTH{1'b0}};
end
else if (write_sce_combi) begin
asmi_sce <= avl_csr_wrdata[2:0];
end
else if (asmi_en4b_addr) begin
asmi_sce <= temp_sce;
end
end
// decoder ring if the CHIP_SEL is only 1 then avalon address is the temp address
// if the chipsele is 2 then need to remove top address bit
// if the chipelect is 3 then remove the top 2 address bits.
assign temp_mem_addr = CHIP_SELS == 1 ? avl_mem_addr:( CHIP_SELS == 2 ? {1'b0,avl_mem_addr[ADDR_WIDTH-2:0]}:{2'b00,avl_mem_addr[ADDR_WIDTH-3:0]});
end
else begin
always @(posedge clk) begin
asmi_sce <= {CS_WIDTH{1'b0}};
end
assign temp_mem_addr = avl_mem_addr;
end
endgenerate
// wait_request generation logic
assign avl_mem_waitrequest = (asmi_busy || asmi_busy_reg) ? 1'b1 : (local_waitrequest || wr_mem_waitrequest);
assign avl_csr_waitrequest = (asmi_busy || asmi_busy_reg) ? 1'b1 : (local_waitrequest || wr_mem_waitrequest);
// access CSR decoding logic
assign access_csr_status = (avl_csr_addr == 3'b000);
assign access_csr_sid = (avl_csr_addr == 3'b001);
assign access_csr_rdid = (avl_csr_addr == 3'b010);
assign access_csr_mem_op = (avl_csr_addr == 3'b011);
assign access_isr = (avl_csr_addr == 3'b100);
assign access_imr = (avl_csr_addr == 3'b101);
assign access_sce = (avl_csr_addr == 3'b110);
// read/write memory combi logic
assign read_mem_combi = (avl_mem_read && ~avl_mem_waitrequest);
assign write_mem_combi = (avl_mem_write && ~avl_mem_waitrequest);
// read csr logic
assign read_status_combi = (avl_csr_read && access_csr_status && ~avl_csr_waitrequest);
assign read_sid_combi = (avl_csr_read && access_csr_sid && ~avl_csr_waitrequest);
assign read_rdid_combi = (avl_csr_read && access_csr_rdid && ~avl_csr_waitrequest);
assign read_isr_combi = (avl_csr_read && access_isr && ~avl_csr_waitrequest);
assign read_imr_combi = (avl_csr_read && access_imr && ~avl_csr_waitrequest);
assign write_isr_combi = (avl_csr_write && access_isr && ~avl_csr_waitrequest);
assign write_imr_combi = (avl_csr_write && access_imr && ~avl_csr_waitrequest);
assign write_sce_combi = (avl_csr_write && access_sce && ~avl_csr_waitrequest);
// write csr logic
assign bulk_erase_combi = (avl_csr_write && access_csr_mem_op && ~avl_csr_waitrequest && avl_csr_wrdata[1:0] == 2'b01);
assign sector_erase_combi = (avl_csr_write && access_csr_mem_op && ~avl_csr_waitrequest && avl_csr_wrdata[1:0] == 2'b10);
assign sector_protect_combi = (avl_csr_write && access_csr_mem_op && ~avl_csr_waitrequest && avl_csr_wrdata[1:0] == 2'b11);
assign illegal_write_combi = (asmi_illegal_write) ? 1'b1 :
(write_isr_combi && avl_csr_wrdata[1]) ? 1'b0 :
illegal_write_reg;
assign illegal_erase_combi = (asmi_illegal_erase) ? 1'b1 :
(write_isr_combi && avl_csr_wrdata[0]) ? 1'b0 :
illegal_erase_reg;
assign m_illegal_write_combi= (write_imr_combi) ? avl_csr_wrdata[1] : m_illegal_write_reg;
assign m_illegal_erase_combi= (write_imr_combi) ? avl_csr_wrdata[0] : m_illegal_erase_reg;
assign wren_combi = (sector_protect_combi || sector_erase_combi || bulk_erase_combi);
assign asmi_rden = (rd_burstcount_cnt > 9'd0); // deasserted at the last 2 byte - refer to ASMI_PARALLEL UG
// interrupt signal
assign irq = (illegal_write_reg && m_illegal_write_reg) || (illegal_erase_reg && m_illegal_erase_reg);
assign last_wr_byte = (wr_burstcount_cnt == wr_mem_burstcount - 9'd1) ? 1'b1 : 1'b0;
assign asmi_wren = wren_internal || asmi_en4b_addr || asmi_shift_bytes || asmi_write;
assign data_valid_combi = (rd_burstcount_cnt[1:0] == 2'b00) ? asmi_data_valid : 1'b0;
assign wfifo_data_in_0 = {avl_mem_byteenable[0], avl_mem_wrdata[7:0] };
assign wfifo_data_in_1 = {avl_mem_byteenable[1], avl_mem_wrdata[15:8] };
assign wfifo_data_in_2 = {avl_mem_byteenable[2], avl_mem_wrdata[23:16] };
assign wfifo_data_in_3 = {avl_mem_byteenable[3], avl_mem_wrdata[31:24] };
assign avl_mem_rddata = {rd_data_reg[3], rd_data_reg[2], rd_data_reg[1], rd_data_reg[0]};
assign pending_wr_data = (|wr_data_reg_full) ? 1'b1 : 1'b0;
assign detect_addroffset = (pending_wr_data && wr_data_reg[wr_cnt][8]) ? 1'b1 :
(wr_burstcount_cnt == {9{1'b0}}) ? 1'b0 : detect_addroffset_reg;
//-------------------------------- array to store write data -------------------------------------
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
wr_data_reg <= '{{9{1'b0}}, {9{1'b0}}, {9{1'b0}}, {9{1'b0}}};
wr_data_reg_full <= {4{1'b0}};
end
else if (write_mem_combi) begin
wr_data_reg <= {wfifo_data_in_3, wfifo_data_in_2, wfifo_data_in_1, wfifo_data_in_0};
wr_data_reg_full <= {4{1'b1}};
end
else if (wr_data_reg_full > 4'b0000) begin
wr_data_reg_full <= wr_data_reg_full << 1;
end
end
//-------------------------------- array to store read data -------------------------------------
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
rd_data_reg <= '{{8{1'b0}}, {8{1'b0}}, {8{1'b0}}, {8{1'b0}}};
rd_cnt <= {2{1'b0}};
end
else if (asmi_data_valid) begin
rd_data_reg[rd_cnt] <= asmi_dataout;
rd_cnt <= rd_cnt + 2'b01;
end
end
//------------------------------- Enable 4-byte addressing out of reset ----------------------
generate
if (ENABLE_4BYTE_ADDR) begin
typedef enum logic[1:0] {EN4B_CHIP1, EN4B_CHIP2, EN4B_CHIP3, IDLE} state_t;
state_t state;
always @(posedge clk or negedge reset_n_reg) begin // use reset_n_reg because user is allow to send cmd to ASMI_PARALLEL 2 clock cycles after reset
if (~reset_n_reg) begin
state <= EN4B_CHIP1;
asmi_en4b_addr <= 1'b1;
temp_sce <= 3'b001;
end
else begin
case (state)
EN4B_CHIP1 : begin
asmi_en4b_addr <= 1'b1;
if (~asmi_busy) begin
if (CHIP_SELS > 1) begin
state <= EN4B_CHIP2;
temp_sce <= 3'b010;
end
else begin
state <= IDLE;
temp_sce <= 3'b000;
end
end
end
EN4B_CHIP2 : begin
asmi_en4b_addr <= 1'b1;
if (~asmi_busy) begin
if (CHIP_SELS > 2) begin
state <= EN4B_CHIP3;
temp_sce <= 3'b100;
end
else begin
state <= IDLE;
temp_sce <= 3'b000;
end
end
end
EN4B_CHIP3 : begin
asmi_en4b_addr <= 1'b1;
if (~asmi_busy) begin
state <= IDLE;
temp_sce <= 3'b000;
end
end
IDLE : begin
asmi_en4b_addr <= 1'b0;
state <= IDLE;
temp_sce <= 3'b000;
end
default : begin
asmi_en4b_addr <= 1'b0;
state <= IDLE;
temp_sce <= 3'b000;
end
endcase
end
end
end
else begin
always @(posedge clk) begin
asmi_en4b_addr <= 1'b0;
temp_sce <= 3'b000;
end
end
endgenerate
//--------------------------------------- Waitrequest logic ----------------------------------
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
wr_mem_waitrequest <= 1'b0;
local_waitrequest <= 1'b0;
end
else begin
if (read_mem_combi || read_status_combi || read_sid_combi || read_rdid_combi || bulk_erase_combi || sector_erase_combi || sector_protect_combi || asmi_en4b_addr) begin // no back pressure during imr & isr access
local_waitrequest <= 1'b1;
end
else if (asmi_busy_reg && ~asmi_busy) begin
local_waitrequest <= 1'b0;
end
if (write_mem_combi) begin
wr_mem_waitrequest <= 1'b1;
end
else if ((~pending_wr_data && ~asmi_write) || asmi_busy_reg && ~asmi_busy) begin
wr_mem_waitrequest <= 1'b0;
end
end
end
// -------------------------------------- MEM ACCESS -----------------------------------------
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
rd_mem_burstcount <= {9{1'b0}};
wr_mem_burstcount <= {9{1'b0}};
wr_mem_addr <= {LOCAL_ADDR_WIDTH{1'b0}};
end
else begin
if (read_mem_combi) begin
rd_mem_burstcount <= {avl_mem_burstcount, 2'b00};
end
if (write_mem_combi && (wr_burstcount_cnt == {9{1'b0}})) begin
wr_mem_addr <= {temp_mem_addr, 2'b00};
wr_mem_burstcount <= {avl_mem_burstcount, 2'b00};
end
end
end
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
wr_burstcount_cnt <= {9{1'b0}};
end
else begin
if (pending_wr_data) begin
wr_burstcount_cnt <= wr_burstcount_cnt + 9'd1;
end
else if (wr_burstcount_cnt == wr_mem_burstcount) begin
wr_burstcount_cnt <= {9{1'b0}};
end
end
end
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
rd_burstcount_cnt <= {9{1'b0}};
end
else begin
if (read_mem_combi) begin
rd_burstcount_cnt <= 9'd1;
end
else if (rd_burstcount_cnt == rd_mem_burstcount) begin // each rd 4 burst
rd_burstcount_cnt <= {9{1'b0}};
end
else if (asmi_data_valid && rd_burstcount_cnt > 0) begin
rd_burstcount_cnt <= rd_burstcount_cnt + 9'd1;
end
end
end
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
asmi_addr <= {ASMI_ADDR_WIDTH{1'b0}};
end
else begin
if (sector_erase_combi) begin // set lower 16 bits to zero so that erase at starting address of each sector
asmi_addr <= {avl_csr_wrdata[LAST_ADDR_BIT : 8], {16{1'b0}}};
end
if (read_mem_combi) begin
asmi_addr <= {temp_mem_addr, 2'b00};
end
if (detect_addroffset && ~detect_addroffset_reg) begin
asmi_addr <= wr_mem_addr + {{LOCAL_ADDR_WIDTH-9{1'b0}}, wr_burstcount_cnt};
end
end
end
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
asmi_datain <= {8{1'b0}};
wr_cnt <= {2{1'b0}};
asmi_shift_bytes <= 1'b0;
end
else begin
if (sector_protect_combi) begin
asmi_datain <= {{1{1'b0}}, avl_csr_wrdata[11], avl_csr_wrdata[12], avl_csr_wrdata[10:8], {2{1'b0}}}; // BP3, TB, BP2, BP1, BP0
end
if (pending_wr_data) begin
asmi_datain <= wr_data_reg[wr_cnt][7:0];
wr_cnt <= wr_cnt + 2'd1;
end
if (pending_wr_data && wr_data_reg[wr_cnt][8]) begin
asmi_shift_bytes <= 1'b1;
end
else begin
asmi_shift_bytes <= 1'b0;
end
end
end
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
asmi_read_status <= 1'b0;
asmi_read_sid <= 1'b0;
asmi_read_rdid <= 1'b0;
asmi_bulk_erase <= 1'b0;
asmi_sector_erase <= 1'b0;
asmi_sector_protect <= 1'b0;
wren_internal <= 1'b0;
asmi_write <= 1'b0;
asmi_fast_read <= 1'b0;
asmi_busy_reg <= 1'b0;
avl_mem_rddata_valid <= 1'b0;
detect_addroffset_reg <= 1'b0;
reset_n_reg <= 1'b0;
end
else begin
asmi_read_status <= read_status_combi;
asmi_read_sid <= read_sid_combi;
asmi_read_rdid <= read_rdid_combi;
asmi_bulk_erase <= bulk_erase_combi;
asmi_sector_erase <= sector_erase_combi;
asmi_sector_protect <= sector_protect_combi;
wren_internal <= wren_combi;
asmi_write <= last_wr_byte;
asmi_fast_read <= read_mem_combi;
asmi_busy_reg <= asmi_busy;
avl_mem_rddata_valid <= data_valid_combi;
detect_addroffset_reg <= detect_addroffset;
reset_n_reg <= 1'b1;
end
end
// --------------------------------------------- CSR ACCESS -------------------------------------
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
illegal_write_reg <= 1'b0;
illegal_erase_reg <= 1'b0;
m_illegal_write_reg <= 1'b0;
m_illegal_erase_reg <= 1'b0;
end
else begin
illegal_write_reg <= illegal_write_combi;
illegal_erase_reg <= illegal_erase_combi;
m_illegal_write_reg <= m_illegal_write_combi;
m_illegal_erase_reg <= m_illegal_erase_combi;
end
end
// csr read only registers enable logic
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
read_status_en <= 1'b0;
read_sid_en <= 1'b0;
read_rdid_en <= 1'b0;
end
else if (asmi_read_status) begin
read_status_en <= 1'b1;
end
else if (asmi_read_sid) begin
read_sid_en <= 1'b1;
end
else if (asmi_read_rdid) begin
read_rdid_en <= 1'b1;
end
else if (asmi_busy == 0) begin
read_status_en <= 1'b0;
read_sid_en <= 1'b0;
read_rdid_en <= 1'b0;
end
end
// generation logic for avl csr read data valid
assign avl_csr_rddata_valid = read_status_valid || read_sid_valid || read_rdid_valid || read_isr_valid || read_imr_valid;
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
read_status_valid <= 1'b0;
read_sid_valid <= 1'b0;
read_rdid_valid <= 1'b0;
read_isr_valid <= 1'b0;
read_imr_valid <= 1'b0;
end
else begin
if (read_status_en && asmi_busy == 0) begin
read_status_valid <= 1'b1;
end
else begin
read_status_valid <= 1'b0;
end
if (read_sid_en && asmi_busy == 0) begin
read_sid_valid <= 1'b1;
end
else begin
read_sid_valid <= 1'b0;
end
if (read_rdid_en && asmi_busy == 0) begin
read_rdid_valid <= 1'b1;
end
else begin
read_rdid_valid <= 1'b0;
end
if (read_isr_combi) begin
read_isr_valid <= 1'b1;
end
else begin
read_isr_valid <= 1'b0;
end
if (read_imr_combi) begin
read_imr_valid <= 1'b1;
end
else begin
read_imr_valid <= 1'b0;
end
end
end
// generation logic for avl csr read data
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
avl_csr_rddata <= {CSR_DATA_WIDTH{1'b0}};
end
else begin
if (read_status_en && asmi_busy == 0) begin
avl_csr_rddata <= {{CSR_DATA_WIDTH-8{1'b0}}, asmi_status_out};
end
if (read_sid_en && asmi_busy == 0) begin
avl_csr_rddata <= {{CSR_DATA_WIDTH-8{1'b0}}, asmi_epcs_id};
end
if (read_rdid_en && asmi_busy == 0) begin
avl_csr_rddata <= {{CSR_DATA_WIDTH-8{1'b0}}, asmi_rdid_out};
end
if (read_isr_combi) begin
avl_csr_rddata <= {{CSR_DATA_WIDTH-2{1'b0}}, illegal_write_reg, illegal_erase_reg};
end
if (read_imr_combi) begin
avl_csr_rddata <= {{CSR_DATA_WIDTH-2{1'b0}}, m_illegal_write_reg, m_illegal_erase_reg};
end
end
end
endmodule

230
ip/altera_epcq_controller_mod/altera_epcq_controller_arb.sv
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@ -1,230 +0,0 @@
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1ps / 1ps
module altera_epcq_controller_arb #(
parameter CS_WIDTH = 1,
parameter ENABLE_4BYTE_ADDR = 1,
parameter ADDR_WIDTH = 22,
parameter ASI_WIDTH = 1,
parameter DEVICE_FAMILY = "CYCLONE V",
parameter ASMI_ADDR_WIDTH = 22,
parameter CHIP_SELS = 1
)(
input wire clk,
input wire reset_n,
// ports to access csr
input wire avl_csr_write,
input wire avl_csr_read,
input wire [2:0] avl_csr_addr,
input wire [31:0] avl_csr_wrdata,
output reg [31:0] avl_csr_rddata,
output reg avl_csr_rddata_valid,
output reg avl_csr_waitrequest,
// ports to access memory
input wire avl_mem_write,
input wire avl_mem_read,
input wire [ADDR_WIDTH-1:0] avl_mem_addr,
input wire [31:0] avl_mem_wrdata,
input wire [3:0] avl_mem_byteenable,
input wire [6:0] avl_mem_burstcount,
output wire [31:0] avl_mem_rddata,
output reg avl_mem_rddata_valid,
output reg avl_mem_waitrequest,
// interrupt signal
output reg irq,
// Disable dedicated active serial interface
input wire [ASI_WIDTH-1:0] epcq_dataout,
output reg epcq_dclk,
output reg [CS_WIDTH-1:0] epcq_scein,
output reg [ASI_WIDTH-1:0] epcq_sdoin,
output reg [ASI_WIDTH-1:0] epcq_dataoe,
// ASMI PARALLEL interface
input wire [ASI_WIDTH-1:0] ddasi_dataoe,
output reg [ASI_WIDTH-1:0] ddasi_dataout,
input wire ddasi_dclk,
input wire [CS_WIDTH-1:0] ddasi_scein,
input reg [ASI_WIDTH-1:0] ddasi_sdoin,
input wire asmi_busy,
input wire asmi_data_valid,
input wire [7:0] asmi_dataout,
output reg asmi_clkin,
output reg asmi_reset,
output reg [CS_WIDTH-1:0] asmi_sce,
output reg [ASMI_ADDR_WIDTH-1:0] asmi_addr,
output reg [7:0] asmi_datain,
output reg asmi_fast_read,
output wire asmi_rden,
output reg asmi_shift_bytes,
output reg asmi_en4b_addr,
output wire asmi_wren,
output reg asmi_write,
input wire asmi_illegal_erase,
input wire asmi_illegal_write,
input wire [7:0] asmi_rdid_out,
input wire [7:0] asmi_status_out,
input wire [7:0] asmi_epcs_id,
output reg asmi_read_rdid,
output reg asmi_read_status,
output reg asmi_read_sid,
output reg asmi_bulk_erase,
output reg asmi_sector_erase,
output reg asmi_sector_protect
);
reg temp_mem_write, temp_mem_read, mem_write, mem_read, back_pressured_ctrl;
reg [ADDR_WIDTH-1:0] temp_mem_addr, mem_addr;
reg [31:0] temp_mem_wrdata, mem_wrdata;
reg [3:0] temp_mem_byteenable, mem_byteenable;
reg [6:0] temp_mem_burstcount, mem_burstcount;
wire back_pressured, temp_csr_waitrequest, temp_mem_waitrequest;
//-------------------- Arbitration logic between avalon csr and mem interface -----------
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
back_pressured_ctrl <= 1'b0;
end
else if (back_pressured) begin
back_pressured_ctrl <= 1'b1;
end
else if (~temp_csr_waitrequest) begin
back_pressured_ctrl <= 1'b0;
end
end
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
mem_write <= 1'b0;
mem_read <= 1'b0;
mem_addr <= {ADDR_WIDTH{1'b0}};
mem_wrdata <= {32{1'b0}};
mem_byteenable <= {4{1'b0}};
mem_burstcount <= {7{1'b0}};
end
else if ((avl_csr_write || avl_csr_read) && ~avl_csr_waitrequest && (avl_mem_write || avl_mem_read) && ~avl_mem_waitrequest) begin
// to back pressure master
mem_write <= avl_mem_write;
mem_read <= avl_mem_read;
mem_addr <= avl_mem_addr;
mem_wrdata <= avl_mem_wrdata;
mem_byteenable <= avl_mem_byteenable;
mem_burstcount <= avl_mem_burstcount;
end
end
assign back_pressured = ((avl_csr_write || avl_csr_read) && ~temp_csr_waitrequest && (avl_mem_write || avl_mem_read)) ? 1'b1 : 1'b0; // to back pressure controller
assign avl_csr_waitrequest = (~avl_csr_write && ~avl_csr_read && back_pressured_ctrl) ? 1'b1 : temp_csr_waitrequest;
assign avl_mem_waitrequest = (back_pressured_ctrl) ? 1'b1 : temp_mem_waitrequest;
assign temp_mem_write = (back_pressured) ? 1'b0 :
(back_pressured_ctrl) ? mem_write : avl_mem_write;
assign temp_mem_read = (back_pressured) ? 1'b0 :
(back_pressured_ctrl) ? mem_read : avl_mem_read;
assign temp_mem_addr = (back_pressured) ? {ADDR_WIDTH{1'b0}} :
(back_pressured_ctrl) ? mem_addr : avl_mem_addr;
assign temp_mem_wrdata = (back_pressured) ? {32{1'b0}} :
(back_pressured_ctrl) ? mem_wrdata : avl_mem_wrdata;
assign temp_mem_byteenable = (back_pressured) ? {4{1'b0}} :
(back_pressured_ctrl) ? mem_byteenable : avl_mem_byteenable;
assign temp_mem_burstcount = (back_pressured) ? {7{1'b0}} :
(back_pressured_ctrl) ? mem_burstcount : avl_mem_burstcount;
//---------------------------------------------------------------------------------------//
altera_epcq_controller #(
.CS_WIDTH (CS_WIDTH),
.DEVICE_FAMILY (DEVICE_FAMILY),
.ADDR_WIDTH (ADDR_WIDTH),
.ASMI_ADDR_WIDTH (ASMI_ADDR_WIDTH),
.ASI_WIDTH (ASI_WIDTH),
.CHIP_SELS (CHIP_SELS),
.ENABLE_4BYTE_ADDR (ENABLE_4BYTE_ADDR)
) controller (
.clk (clk),
.reset_n (reset_n),
.avl_csr_read (avl_csr_read),
.avl_csr_waitrequest (temp_csr_waitrequest),
.avl_csr_write (avl_csr_write),
.avl_csr_addr (avl_csr_addr),
.avl_csr_wrdata (avl_csr_wrdata),
.avl_csr_rddata (avl_csr_rddata),
.avl_csr_rddata_valid (avl_csr_rddata_valid),
.avl_mem_write (temp_mem_write),
.avl_mem_burstcount (temp_mem_burstcount),
.avl_mem_waitrequest (temp_mem_waitrequest),
.avl_mem_read (temp_mem_read),
.avl_mem_addr (temp_mem_addr),
.avl_mem_wrdata (temp_mem_wrdata),
.avl_mem_byteenable (temp_mem_byteenable),
.avl_mem_rddata (avl_mem_rddata),
.avl_mem_rddata_valid (avl_mem_rddata_valid),
.asmi_status_out (asmi_status_out),
.asmi_epcs_id (asmi_epcs_id),
.asmi_illegal_erase (asmi_illegal_erase),
.asmi_illegal_write (asmi_illegal_write),
.ddasi_dataoe (ddasi_dataoe),
.ddasi_dclk (ddasi_dclk),
.ddasi_scein (ddasi_scein),
.ddasi_sdoin (ddasi_sdoin),
.asmi_busy (asmi_busy),
.asmi_data_valid (asmi_data_valid),
.asmi_dataout (asmi_dataout),
.epcq_dataout (epcq_dataout),
.ddasi_dataout (ddasi_dataout),
.asmi_read_rdid (asmi_read_rdid),
.asmi_read_status (asmi_read_status),
.asmi_read_sid (asmi_read_sid),
.asmi_bulk_erase (asmi_bulk_erase),
.asmi_sector_erase (asmi_sector_erase),
.asmi_sector_protect (asmi_sector_protect),
.epcq_dclk (epcq_dclk),
.epcq_scein (epcq_scein),
.epcq_sdoin (epcq_sdoin),
.epcq_dataoe (epcq_dataoe),
.asmi_clkin (asmi_clkin),
.asmi_reset (asmi_reset),
.asmi_sce (asmi_sce),
.asmi_addr (asmi_addr),
.asmi_datain (asmi_datain),
.asmi_fast_read (asmi_fast_read),
.asmi_rden (asmi_rden),
.asmi_shift_bytes (asmi_shift_bytes),
.asmi_wren (asmi_wren),
.asmi_write (asmi_write),
.asmi_rdid_out (asmi_rdid_out),
.asmi_en4b_addr (asmi_en4b_addr),
.irq (irq)
);
endmodule

176
ip/altera_epcq_controller_mod/altera_epcq_controller_fifo.v
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@ -1,176 +0,0 @@
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: altera_epcq_controller_fifo.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.1.0 Internal Build 64 05/14/2014 PN Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_epcq_controller_fifo #(
parameter DEVICE_FAMILY = "CYCLONE V",
parameter MEMORY_TYPE = "RAM_BLOCK_TYPE=MLAB"
)(
clock,
data,
rdreq,
wrreq,
empty,
full,
q);
input clock;
input [35:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [35:0] q;
wire sub_wire0;
wire sub_wire1;
wire [35:0] sub_wire2;
wire empty = sub_wire0;
wire full = sub_wire1;
wire [35:0] q = sub_wire2[35:0];
scfifo scfifo_component (
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.full (sub_wire1),
.q (sub_wire2),
.aclr (),
.almost_empty (),
.almost_full (),
.sclr (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = DEVICE_FAMILY,
scfifo_component.lpm_hint = MEMORY_TYPE,
scfifo_component.lpm_numwords = 1024,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 36,
scfifo_component.lpm_widthu = 10,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "1024"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "8"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "8"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M9K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf

453
ip/altera_epcq_controller_mod/altera_epcq_controller_hw.tcl
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@ -1,453 +0,0 @@
# (C) 2001-2015 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and other
# software and tools, and its AMPP partner logic functions, and any output
# files any of the foregoing (including device programming or simulation
# files), and any associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License Subscription
# Agreement, Altera MegaCore Function License Agreement, or other applicable
# license agreement, including, without limitation, that your use is for the
# sole purpose of programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the applicable
# agreement for further details.
# TCL File Generated by Component Editor 14.1
# Fri May 09 18:08:10 MYT 2014
# DO NOT MODIFY
#
# altera_epcq_controller_core "Altera EPCQ Serial Flash controller core" v14.1
# Altera Coorperation 2014.05.23.15:01:29
# This component is a serial flash controller which allows user to access Altera EPCQ devices
#
#
# request TCL package from ACDS 14.1
#
package require -exact qsys 14.1
#
# module altera_epcq_controller
#
set_module_property DESCRIPTION "This component is a serial flash controller which allows user to access Altera EPCQ devices"
set_module_property NAME altera_epcq_controller_core
set_module_property VERSION 19.1
set_module_property INTERNAL true
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR "Altera Corporation"
set_module_property DISPLAY_NAME "Altera EPCQ Serial Flash controller core"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property HIDE_FROM_QUARTUS true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
set_module_property VALIDATION_CALLBACK "validate"
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL altera_epcq_controller_arb
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file altera_epcq_controller_arb.sv SYSTEM_VERILOG PATH altera_epcq_controller_arb.sv TOP_LEVEL_FILE
add_fileset_file altera_epcq_controller.sv SYSTEM_VERILOG PATH altera_epcq_controller.sv
add_fileset SIM_VERILOG SIM_VERILOG "" ""
set_fileset_property SIM_VERILOG TOP_LEVEL altera_epcq_controller_arb
set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file altera_epcq_controller_arb.sv SYSTEM_VERILOG PATH altera_epcq_controller_arb.sv TOP_LEVEL_FILE
add_fileset_file altera_epcq_controller.sv SYSTEM_VERILOG PATH altera_epcq_controller.sv
#
# add system info parameter
add_parameter deviceFeaturesSystemInfo STRING "None"
set_parameter_property deviceFeaturesSystemInfo system_info "DEVICE_FEATURES"
set_parameter_property deviceFeaturesSystemInfo VISIBLE false
#
# parameters
#
add_parameter DEVICE_FAMILY STRING ""
set_parameter_property DEVICE_FAMILY SYSTEM_INFO "DEVICE_FAMILY"
set_parameter_property DEVICE_FAMILY HDL_PARAMETER true
set_parameter_property DEVICE_FAMILY VISIBLE false
add_parameter ADDR_WIDTH INTEGER 19
set_parameter_property ADDR_WIDTH DEFAULT_VALUE 19
set_parameter_property ADDR_WIDTH DISPLAY_NAME ADDR_WIDTH
set_parameter_property ADDR_WIDTH DERIVED true
set_parameter_property ADDR_WIDTH TYPE INTEGER
set_parameter_property ADDR_WIDTH VISIBLE false
set_parameter_property ADDR_WIDTH UNITS None
set_parameter_property ADDR_WIDTH ALLOWED_RANGES {19, 20, 21, 22, 23, 24, 25, 26, 27, 28}
set_parameter_property ADDR_WIDTH HDL_PARAMETER true
add_parameter ASMI_ADDR_WIDTH INTEGER 24
set_parameter_property ASMI_ADDR_WIDTH DEFAULT_VALUE 24
set_parameter_property ASMI_ADDR_WIDTH DISPLAY_NAME ASMI_ADDR_WIDTH
set_parameter_property ASMI_ADDR_WIDTH DERIVED true
set_parameter_property ASMI_ADDR_WIDTH TYPE INTEGER
set_parameter_property ASMI_ADDR_WIDTH VISIBLE false
set_parameter_property ASMI_ADDR_WIDTH UNITS None
set_parameter_property ASMI_ADDR_WIDTH ALLOWED_RANGES {24, 32}
set_parameter_property ASMI_ADDR_WIDTH HDL_PARAMETER true
add_parameter ASI_WIDTH INTEGER 1
set_parameter_property ASI_WIDTH DEFAULT_VALUE 1
set_parameter_property ASI_WIDTH DISPLAY_NAME ASI_WIDTH
set_parameter_property ASI_WIDTH DERIVED true
set_parameter_property ASI_WIDTH TYPE INTEGER
set_parameter_property ASI_WIDTH VISIBLE false
set_parameter_property ASI_WIDTH UNITS None
set_parameter_property ASI_WIDTH ALLOWED_RANGES {1, 4}
set_parameter_property ASI_WIDTH HDL_PARAMETER true
add_parameter CS_WIDTH INTEGER 1
set_parameter_property CS_WIDTH DEFAULT_VALUE 1
set_parameter_property CS_WIDTH DISPLAY_NAME CS_WIDTH
set_parameter_property CS_WIDTH DERIVED true
set_parameter_property CS_WIDTH TYPE INTEGER
set_parameter_property CS_WIDTH VISIBLE false
set_parameter_property CS_WIDTH UNITS None
set_parameter_property CS_WIDTH ALLOWED_RANGES {1, 3}
set_parameter_property CS_WIDTH HDL_PARAMETER true
add_parameter CHIP_SELS INTEGER "1"
set_parameter_property CHIP_SELS DISPLAY_NAME "Number of Chip Selects used"
set_parameter_property CHIP_SELS ALLOWED_RANGES {1 2 3}
set_parameter_property CHIP_SELS DESCRIPTION "Number of EPCQ(L) devices that are attached and need a CHIPSEL"
set_parameter_property CHIP_SELS HDL_PARAMETER true
set_parameter_property CHIP_SELS AFFECTS_GENERATION true
add_parameter DDASI INTEGER "0"
set_parameter_property DDASI DISPLAY_NAME "Disable dedicated Active Serial interface"
set_parameter_property DDASI DESCRIPTION "Check to route ASMIBLOCK signals to top level of design"
set_parameter_property DDASI AFFECTS_GENERATION true
set_parameter_property DDASI VISIBLE false
set_parameter_property DDASI DERIVED false
add_parameter ENABLE_4BYTE_ADDR INTEGER "0"
set_parameter_property ENABLE_4BYTE_ADDR DISPLAY_NAME "Enable 4-byte addressing mode"
set_parameter_property ENABLE_4BYTE_ADDR DESCRIPTION "Check to enable 4-byte addressing mode for device larger than 128Mbyte"
set_parameter_property ENABLE_4BYTE_ADDR AFFECTS_GENERATION true
set_parameter_property ENABLE_4BYTE_ADDR VISIBLE false
set_parameter_property ENABLE_4BYTE_ADDR HDL_PARAMETER true
set_parameter_property ENABLE_4BYTE_ADDR DERIVED true
# SPI device selection
add_parameter FLASH_TYPE STRING "EPCQ16"
set_parameter_property FLASH_TYPE DISPLAY_NAME "Configuration device type"
set_parameter_property FLASH_TYPE DESCRIPTION "Select targeted EPCS/EPCQ devices"
set_parameter_property FLASH_TYPE AFFECTS_GENERATION true
set_parameter_property FLASH_TYPE VISIBLE true
set_parameter_property FLASH_TYPE DERIVED false
add_parameter IO_MODE STRING "STANDARD"
set_parameter_property IO_MODE DISPLAY_NAME "Choose I/O mode"
set_parameter_property IO_MODE ALLOWED_RANGES {"STANDARD" "QUAD"}
set_parameter_property IO_MODE DESCRIPTION "Select extended data width when Fast Read operation is enabled"
#
# display items
#
#
# connection point clock_sink
#
add_interface clock_sink clock end
set_interface_property clock_sink clockRate 0
set_interface_property clock_sink ENABLED true
set_interface_property clock_sink EXPORT_OF ""
set_interface_property clock_sink PORT_NAME_MAP ""
set_interface_property clock_sink CMSIS_SVD_VARIABLES ""
set_interface_property clock_sink SVD_ADDRESS_GROUP ""
add_interface_port clock_sink clk clk Input 1
#
# connection point reset
#
add_interface reset reset end
set_interface_property reset associatedClock clock_sink
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""
add_interface_port reset reset_n reset_n Input 1
#
# connection point avl_csr
#
add_interface avl_csr avalon end
set_interface_property avl_csr addressUnits WORDS
set_interface_property avl_csr associatedClock clock_sink
set_interface_property avl_csr associatedReset reset
set_interface_property avl_csr bitsPerSymbol 8
set_interface_property avl_csr burstOnBurstBoundariesOnly false
set_interface_property avl_csr burstcountUnits WORDS
set_interface_property avl_csr explicitAddressSpan 0
set_interface_property avl_csr holdTime 0
set_interface_property avl_csr linewrapBursts false
set_interface_property avl_csr maximumPendingReadTransactions 1
set_interface_property avl_csr maximumPendingWriteTransactions 0
set_interface_property avl_csr readLatency 0
set_interface_property avl_csr readWaitTime 0
set_interface_property avl_csr setupTime 0
set_interface_property avl_csr timingUnits Cycles
set_interface_property avl_csr writeWaitTime 0
set_interface_property avl_csr ENABLED true
set_interface_property avl_csr EXPORT_OF ""
set_interface_property avl_csr PORT_NAME_MAP ""
set_interface_property avl_csr CMSIS_SVD_VARIABLES ""
set_interface_property avl_csr SVD_ADDRESS_GROUP ""
add_interface_port avl_csr avl_csr_read read Input 1
add_interface_port avl_csr avl_csr_waitrequest waitrequest Output 1
add_interface_port avl_csr avl_csr_write write Input 1
add_interface_port avl_csr avl_csr_addr address Input 3
add_interface_port avl_csr avl_csr_wrdata writedata Input 32
add_interface_port avl_csr avl_csr_rddata readdata Output 32
add_interface_port avl_csr avl_csr_rddata_valid readdatavalid Output 1
#
# connection point avl_mem
#
add_interface avl_mem avalon end
set_interface_property avl_mem addressUnits WORDS
set_interface_property avl_mem associatedClock clock_sink
set_interface_property avl_mem associatedReset reset
set_interface_property avl_mem bitsPerSymbol 8
set_interface_property avl_mem burstOnBurstBoundariesOnly false
set_interface_property avl_mem burstcountUnits WORDS
set_interface_property avl_mem explicitAddressSpan 0
set_interface_property avl_mem holdTime 0
set_interface_property avl_mem linewrapBursts true
set_interface_property avl_mem maximumPendingReadTransactions 1
set_interface_property avl_mem maximumPendingWriteTransactions 0
set_interface_property avl_mem constantBurstBehavior true
set_interface_property avl_mem readLatency 0
set_interface_property avl_mem readWaitTime 0
set_interface_property avl_mem setupTime 0
set_interface_property avl_mem timingUnits Cycles
set_interface_property avl_mem writeWaitTime 0
set_interface_property avl_mem ENABLED true
set_interface_property avl_mem EXPORT_OF ""
set_interface_property avl_mem PORT_NAME_MAP ""
set_interface_property avl_mem CMSIS_SVD_VARIABLES ""
set_interface_property avl_mem SVD_ADDRESS_GROUP ""
add_interface_port avl_mem avl_mem_write write Input 1
add_interface_port avl_mem avl_mem_burstcount burstcount Input 7
add_interface_port avl_mem avl_mem_waitrequest waitrequest Output 1
add_interface_port avl_mem avl_mem_read read Input 1
add_interface_port avl_mem avl_mem_addr address Input ADDR_WIDTH
add_interface_port avl_mem avl_mem_wrdata writedata Input 32
add_interface_port avl_mem avl_mem_rddata readdata Output 32
add_interface_port avl_mem avl_mem_rddata_valid readdatavalid Output 1
add_interface_port avl_mem avl_mem_byteenable byteenable Input 4
#
# connection point conduit_out
#
add_interface asmi_status_out conduit end
add_interface_port asmi_status_out asmi_status_out conduit_status_out Input 8
add_interface asmi_epcs_id conduit end
add_interface_port asmi_epcs_id asmi_epcs_id conduit_epcs_id Input 8
add_interface asmi_illegal_erase conduit end
add_interface_port asmi_illegal_erase asmi_illegal_erase conduit_illegal_erase Input 1
add_interface asmi_illegal_write conduit end
add_interface_port asmi_illegal_write asmi_illegal_write conduit_illegal_write Input 1
add_interface ddasi_dataoe conduit end
add_interface_port ddasi_dataoe ddasi_dataoe conduit_ddasi_dataoe Input ASI_WIDTH
add_interface ddasi_dclk conduit end
add_interface_port ddasi_dclk ddasi_dclk conduit_ddasi_dclk Input 1
add_interface ddasi_scein conduit end
add_interface_port ddasi_scein ddasi_scein conduit_ddasi_scein Input CS_WIDTH
add_interface ddasi_sdoin conduit end
add_interface_port ddasi_sdoin ddasi_sdoin conduit_ddasi_sdoin Input ASI_WIDTH
add_interface asmi_busy conduit end
add_interface_port asmi_busy asmi_busy conduit_busy Input 1
add_interface asmi_data_valid conduit end
add_interface_port asmi_data_valid asmi_data_valid conduit_data_valid Input 1
add_interface asmi_dataout conduit end
add_interface_port asmi_dataout asmi_dataout conduit_dataout Input 8
add_interface epcq_dataout conduit end
add_interface_port epcq_dataout epcq_dataout conduit_epcq_dataout Input ASI_WIDTH
add_interface ddasi_dataout conduit end
add_interface_port ddasi_dataout ddasi_dataout conduit_ddasi_dataout Output ASI_WIDTH
add_interface asmi_read_rdid conduit end
add_interface_port asmi_read_rdid asmi_read_rdid conduit_read_rdid Output 1
add_interface asmi_read_status conduit end
add_interface_port asmi_read_status asmi_read_status conduit_read_status Output 1
add_interface asmi_read_sid conduit end
add_interface_port asmi_read_sid asmi_read_sid conduit_read_sid Output 1
add_interface asmi_bulk_erase conduit end
add_interface_port asmi_bulk_erase asmi_bulk_erase conduit_bulk_erase Output 1
add_interface asmi_sector_erase conduit end
add_interface_port asmi_sector_erase asmi_sector_erase conduit_sector_erase Output 1
add_interface asmi_sector_protect conduit end
add_interface_port asmi_sector_protect asmi_sector_protect conduit_sector_protect Output 1
add_interface epcq_dclk conduit end
add_interface_port epcq_dclk epcq_dclk conduit_epcq_dclk Output 1
add_interface epcq_scein conduit end
add_interface_port epcq_scein epcq_scein conduit_epcq_scein Output CS_WIDTH
add_interface epcq_sdoin conduit end
add_interface_port epcq_sdoin epcq_sdoin conduit_epcq_sdoin Output ASI_WIDTH
add_interface epcq_dataoe conduit end
add_interface_port epcq_dataoe epcq_dataoe conduit_epcq_dataoe Output ASI_WIDTH
add_interface asmi_clkin conduit end
add_interface_port asmi_clkin asmi_clkin conduit_clkin Output 1
add_interface asmi_reset conduit end
add_interface_port asmi_reset asmi_reset conduit_reset Output 1
add_interface asmi_sce conduit end
add_interface_port asmi_sce asmi_sce conduit_asmi_sce Output CS_WIDTH
add_interface asmi_addr conduit end
add_interface_port asmi_addr asmi_addr conduit_addr Output ASMI_ADDR_WIDTH
add_interface asmi_datain conduit end
add_interface_port asmi_datain asmi_datain conduit_datain Output 8
add_interface asmi_fast_read conduit end
add_interface_port asmi_fast_read asmi_fast_read conduit_fast_read Output 1
add_interface asmi_rden conduit end
add_interface_port asmi_rden asmi_rden conduit_rden Output 1
add_interface asmi_shift_bytes conduit end
add_interface_port asmi_shift_bytes asmi_shift_bytes conduit_shift_bytes Output 1
add_interface asmi_wren conduit end
add_interface_port asmi_wren asmi_wren conduit_wren Output 1
add_interface asmi_write conduit end
add_interface_port asmi_write asmi_write conduit_write Output 1
add_interface asmi_rdid_out conduit end
add_interface_port asmi_rdid_out asmi_rdid_out conduit_rdid_out Input 8
add_interface asmi_en4b_addr conduit end
add_interface_port asmi_en4b_addr asmi_en4b_addr conduit_en4b_addr Output 1
#
# connection point interrupt_sender
#
add_interface interrupt_sender interrupt end
set_interface_property interrupt_sender associatedAddressablePoint avl_csr
set_interface_property interrupt_sender associatedClock clock_sink
set_interface_property interrupt_sender associatedReset reset
set_interface_property interrupt_sender bridgedReceiverOffset ""
set_interface_property interrupt_sender bridgesToReceiver ""
set_interface_property interrupt_sender ENABLED true
set_interface_property interrupt_sender EXPORT_OF ""
set_interface_property interrupt_sender PORT_NAME_MAP ""
set_interface_property interrupt_sender CMSIS_SVD_VARIABLES ""
set_interface_property interrupt_sender SVD_ADDRESS_GROUP ""
add_interface_port interrupt_sender irq irq Output 1
proc validate {} {
set all_supported_SPI_list {"EPCS16" "EPCS64" "EPCS128" "EPCQ16" "EPCQ32" "EPCQ64" "EPCQ128" "EPCQ256" \
"EPCQ512" "EPCQL256" "EPCQL512" "EPCQL1024"}
set_parameter_property FLASH_TYPE "ALLOWED_RANGES" $all_supported_SPI_list
set DEVICE_FAMILY [ get_parameter_value DEVICE_FAMILY ]
set CHIP_SELS [ get_parameter_value CHIP_SELS]
set temp_addr_width [ proc_get_derive_addr_width [ get_parameter_value FLASH_TYPE ] ]
set_parameter_value ENABLE_4BYTE_ADDR [ proc_get_derive_enable_2byte_addr [ get_parameter_value FLASH_TYPE ] ]
if { [ get_parameter_value ENABLE_4BYTE_ADDR ] } {
set_parameter_value ASMI_ADDR_WIDTH 32
} else {
set_parameter_value ASMI_ADDR_WIDTH 24
}
# check whether devices supporting multiple flash - only for Arria 10
if {[check_device_family_equivalence $DEVICE_FAMILY "Arria 10"]} {
set is_multi_flash_support "true"
if {$CHIP_SELS eq 3 } {set_parameter_value ADDR_WIDTH [ expr $temp_addr_width + 2]}
if {$CHIP_SELS eq 2 } {set_parameter_value ADDR_WIDTH [ expr $temp_addr_width + 1]}
if {$CHIP_SELS eq 1 } {set_parameter_value ADDR_WIDTH $temp_addr_width }
} else {
set is_multi_flash_support "false"
set_parameter_value ADDR_WIDTH $temp_addr_width
}
}
proc proc_get_derive_enable_2byte_addr {flash_type} {
if { [ string match "*256*" "$flash_type" ] || [ string match "*512*" "$flash_type" ] || [ string match "*1024*" "$flash_type" ]} {
return true
} else {
return false
}
}
proc proc_get_derive_addr_width {flash_type} {
switch $flash_type {
"EPCS16" - "EPCQ16" {
return 19
}
"EPCS64" - "EPCQ64" {
return 21
}
"EPCS128" - "EPCQ128" {
return 22
}
"EPCQ32" {
return 20
}
"EPCQ256" - "EPCQL256" {
return 23
}
"EPCQ512" - "EPCQL512" {
return 24
}
"EPCQL1024" {
return 25
}
default {
# Should never enter this function
send_message error "$flash_type is not a valid flash type"
}
}
}

58
ip/altera_epcq_controller_mod/altera_epcq_controller_sw.tcl
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@ -1,58 +0,0 @@
# (C) 2001-2015 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and other
# software and tools, and its AMPP partner logic functions, and any output
# files any of the foregoing (including device programming or simulation
# files), and any associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License Subscription
# Agreement, Altera MegaCore Function License Agreement, or other applicable
# license agreement, including, without limitation, that your use is for the
# sole purpose of programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the applicable
# agreement for further details.
#
# altera_epcq_controller_sw.tcl
#
# Create a new driver
create_driver altera_epcq_controller_mod_driver
# Associate it with some hardware known as "altera_epcq_controller"
set_sw_property hw_class_name altera_epcq_controller_mod
# The version of this driver
set_sw_property version 14.1
# This driver may be incompatible with versions of hardware less
# than specified below. Updates to hardware and device drivers
# rendering the driver incompatible with older versions of
# hardware are noted with this property assignment.
set_sw_property min_compatible_hw_version 14.1
# Initialize the driver in alt_sys_init()
set_sw_property auto_initialize true
# This driver only works when the following combinations of interfaces
# are enabled and connected as a group of CSR interfaces.
set_sw_property csr_interfaces "avl_mem,avl_csr"
# The EPCQ interrupt has an interrupt but it is not used in the driver.
# These assignments are still required by the Nios II SBT
set_sw_property isr_preemption_supported true
set_sw_property supported_interrupt_apis "legacy_interrupt_api enhanced_interrupt_api"
# Location in generated BSP that above sources will be copied into
set_sw_property bsp_subdirectory drivers
# Header files
add_sw_property include_source HAL/inc/altera_epcq_controller_mod.h
add_sw_property include_source inc/altera_epcq_controller_mod_regs.h
# C/C++ source files
add_sw_property c_source HAL/src/altera_epcq_controller_mod.c
# This driver supports HAL & UCOSII BSP (OS) types
add_sw_property supported_bsp_type HAL
add_sw_property supported_bsp_type UCOSII

248
ip/altera_epcq_controller_mod/altera_epcq_controller_wrapper.sv.terp
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@ -1,248 +0,0 @@
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1ps / 1ps
${MULTICHIP}
${DDASI_ON}
${SID_EN}
${BULK_ERASE_EN}
${4BYTE_ADDR_EN}
module altera_epcq_controller_wrapper #(
parameter CS_WIDTH = 1,
parameter DEVICE_FAMILY = "Arria V",
parameter ADDR_WIDTH = 24,
parameter ASI_WIDTH = 1,
parameter ENABLE_4BYTE_ADDR = 1,
parameter ASMI_ADDR_WIDTH = 22,
parameter CHIP_SELS = 1
)(
input wire clk,
input wire reset_n,
// ports to access csr
input wire avl_csr_write,
input wire avl_csr_read,
input wire [2:0] avl_csr_addr,
input wire [31:0] avl_csr_wrdata,
output wire [31:0] avl_csr_rddata,
output wire avl_csr_rddata_valid,
output wire avl_csr_waitrequest,
// ports to access memory
input wire avl_mem_write,
input wire avl_mem_read,
input wire [ADDR_WIDTH-1:0] avl_mem_addr,
input wire [31:0] avl_mem_wrdata,
input wire [6:0] avl_mem_burstcount,
input wire [3:0] avl_mem_byteenable,
output wire [31:0] avl_mem_rddata,
output wire avl_mem_rddata_valid,
output wire avl_mem_waitrequest,
`ifdef DDASI_ON
output wire [ASI_WIDTH-1:0] epcq_dataout,
output wire epcq_dclk,
output wire [CS_WIDTH-1:0] epcq_scein,
output wire [ASI_WIDTH-1:0] epcq_sdoin,
output wire [ASI_WIDTH-1:0] epcq_dataoe,
`endif
// interrupt signal
output reg irq
);
`ifdef DDASI_ON
wire [ASI_WIDTH-1:0] ddasi_dataoe;
wire [ASI_WIDTH-1:0] ddasi_dataout;
wire ddasi_dclk;
wire [CS_WIDTH-1:0] ddasi_scein;
wire [ASI_WIDTH-1:0] ddasi_sdoin;
`endif
wire asmi_busy;
wire asmi_data_valid;
wire [7:0] asmi_dataout;
wire asmi_clkin;
wire asmi_reset;
`ifdef MULTICHIP
wire [CS_WIDTH-1:0] asmi_sce;
`endif
wire [ASMI_ADDR_WIDTH-1:0] asmi_addr;
wire [7:0] asmi_datain;
wire asmi_fast_read;
wire asmi_rden;
wire asmi_shift_bytes;
wire asmi_wren;
wire asmi_write;
wire asmi_illegal_erase;
wire asmi_illegal_write;
wire [7:0] asmi_rdid_out;
wire [7:0] asmi_status_out;
`ifdef ENABLE_SID
wire [7:0] asmi_epcs_id;
`endif
wire asmi_read_rdid;
wire asmi_read_status;
wire asmi_read_sid;
`ifdef ENABLE_4BYTE_ADDR_CODE
wire asmi_en4b_addr;
`endif
`ifdef ENABLE_BULK_ERASE
wire asmi_bulk_erase;
`endif
wire asmi_sector_erase;
wire asmi_sector_protect;
altera_epcq_controller_core #(
.DEVICE_FAMILY (DEVICE_FAMILY),
.ADDR_WIDTH (ADDR_WIDTH),
.ASI_WIDTH (ASI_WIDTH),
.ASMI_ADDR_WIDTH (ASMI_ADDR_WIDTH),
.CS_WIDTH (CS_WIDTH),
.ENABLE_4BYTE_ADDR (ENABLE_4BYTE_ADDR),
.CHIP_SELS (CHIP_SELS)
) epcq_controller_inst (
.clk (clk ),
.reset_n (reset_n ),
.avl_csr_write (avl_csr_write ),
.avl_csr_read (avl_csr_read ),
.avl_csr_addr (avl_csr_addr ),
.avl_csr_wrdata (avl_csr_wrdata ),
.avl_csr_rddata (avl_csr_rddata ),
.avl_csr_rddata_valid (avl_csr_rddata_valid ),
.avl_csr_waitrequest (avl_csr_waitrequest ),
.avl_mem_write (avl_mem_write ),
.avl_mem_read (avl_mem_read ),
.avl_mem_addr (avl_mem_addr ),
.avl_mem_wrdata (avl_mem_wrdata ),
.avl_mem_burstcount (avl_mem_burstcount ),
.avl_mem_byteenable (avl_mem_byteenable ),
.avl_mem_rddata (avl_mem_rddata ),
.avl_mem_rddata_valid (avl_mem_rddata_valid ),
.avl_mem_waitrequest (avl_mem_waitrequest ),
.irq (irq ),
`ifdef DDASI_ON
.epcq_dataout (epcq_dataout ),
.epcq_dclk (epcq_dclk ),
.epcq_scein (epcq_scein ),
.epcq_sdoin (epcq_sdoin ),
.epcq_dataoe (epcq_dataoe ),
.ddasi_dataoe (ddasi_dataoe ),
.ddasi_dataout (ddasi_dataout ),
.ddasi_dclk (ddasi_dclk ),
.ddasi_scein (ddasi_scein ),
.ddasi_sdoin (ddasi_sdoin ),
`else
.epcq_dataout ({ASI_WIDTH{1'b0}} ),
.epcq_dclk ( ),
.epcq_scein ( ),
.epcq_sdoin ( ),
.epcq_dataoe ( ),
.ddasi_dataoe ({ASI_WIDTH{1'b0}} ),
.ddasi_dataout ( ),
.ddasi_dclk (1'b0 ),
.ddasi_scein ({CS_WIDTH{1'b0}} ),
.ddasi_sdoin ({ASI_WIDTH{1'b0}} ),
`endif
.asmi_busy (asmi_busy ),
.asmi_data_valid (asmi_data_valid ),
.asmi_dataout (asmi_dataout ),
.asmi_clkin (asmi_clkin ),
.asmi_reset (asmi_reset ),
`ifdef MULTICHIP
.asmi_sce (asmi_sce ),
`else
.asmi_sce ( ),
`endif
.asmi_addr (asmi_addr ),
.asmi_datain (asmi_datain ),
.asmi_fast_read (asmi_fast_read ),
.asmi_rden (asmi_rden ),
.asmi_shift_bytes (asmi_shift_bytes ),
.asmi_wren (asmi_wren ),
.asmi_write (asmi_write ),
.asmi_illegal_erase (asmi_illegal_erase ),
.asmi_illegal_write (asmi_illegal_write ),
.asmi_rdid_out (asmi_rdid_out ),
.asmi_status_out (asmi_status_out ),
`ifdef ENABLE_SID
.asmi_epcs_id (asmi_epcs_id ),
.asmi_read_sid (asmi_read_sid ),
`else
.asmi_epcs_id ({8{1'b0}} ),
.asmi_read_sid ( ),
`endif
.asmi_read_rdid (asmi_read_rdid ),
.asmi_read_status (asmi_read_status ),
`ifdef ENABLE_4BYTE_ADDR_CODE
.asmi_en4b_addr (asmi_en4b_addr ),
`else
.asmi_en4b_addr ( ),
`endif
`ifdef ENABLE_BULK_ERASE
.asmi_bulk_erase (asmi_bulk_erase ),
`else
.asmi_bulk_erase ( ),
`endif
.asmi_sector_erase (asmi_sector_erase ),
.asmi_sector_protect (asmi_sector_protect )
);
altera_asmi_parallel asmi_parallel_inst (
.busy (asmi_busy ),
.data_valid (asmi_data_valid ),
.dataout (asmi_dataout ),
.clkin (asmi_clkin ),
.reset (asmi_reset ),
`ifdef MULTICHIP
.sce (asmi_sce ),
`endif
.addr (asmi_addr ),
.datain (asmi_datain ),
.fast_read (asmi_fast_read ),
.rden (asmi_rden ),
.shift_bytes (asmi_shift_bytes ),
.wren (asmi_wren ),
.write (asmi_write ),
.illegal_erase (asmi_illegal_erase ),
.illegal_write (asmi_illegal_write ),
.rdid_out (asmi_rdid_out ),
.status_out (asmi_status_out ),
.read_dummyclk (1'b0),
`ifdef ENABLE_SID
.epcs_id (asmi_epcs_id ),
.read_sid (asmi_read_sid ),
`endif
.read_rdid (asmi_read_rdid ),
.read_status (asmi_read_status ),
`ifdef ENABLE_4BYTE_ADDR_CODE
.en4b_addr (asmi_en4b_addr ),
`endif
`ifdef ENABLE_BULK_ERASE
.bulk_erase (asmi_bulk_erase ),
`endif
`ifdef DDASI_ON
.asmi_dataoe (ddasi_dataoe ),
.asmi_dataout (ddasi_dataout ),
.asmi_dclk (ddasi_dclk ),
.asmi_scein (ddasi_scein ),
.asmi_sdoin (ddasi_sdoin )
`endif
.sector_erase (asmi_sector_erase ),
.sector_protect (asmi_sector_protect )
);
endmodule

648
ip/altera_epcq_controller_mod/altera_epcq_controller_wrapper_hw.tcl
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@ -1,648 +0,0 @@
# (C) 2001-2015 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and other
# software and tools, and its AMPP partner logic functions, and any output
# files any of the foregoing (including device programming or simulation
# files), and any associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License Subscription
# Agreement, Altera MegaCore Function License Agreement, or other applicable
# license agreement, including, without limitation, that your use is for the
# sole purpose of programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the applicable
# agreement for further details.
package require -exact qsys 14.1
package require -exact altera_terp 1.0
#
# module altera_trace_wrapper
#
set_module_property DESCRIPTION "This component is a serial flash controller which allows user to access Altera EPCQ devices"
set_module_property NAME altera_epcq_controller_mod
set_module_property VERSION 19.1
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP "Basic Functions/Configuration and Programming"
set_module_property AUTHOR "Altera Corporation"
set_module_property DISPLAY_NAME "Altera Serial Flash Controller"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property HIDE_FROM_QUARTUS true
set_module_property EDITABLE true
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
set_module_property ELABORATION_CALLBACK elaboration
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH add_topwrapper_fileset_proc
set_fileset_property QUARTUS_SYNTH TOP_LEVEL altera_epcq_controller_wrapper
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset SIM_VERILOG SIM_VERILOG add_topwrapper_fileset_proc
set_fileset_property SIM_VERILOG TOP_LEVEL altera_epcq_controller_wrapper
set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE true
#
# parameters
#
# +-----------------------------------
# | device family info
# +-----------------------------------
set all_supported_device_families_list {"Arria 10" "Cyclone V" "Arria V GZ" "Arria V" "Stratix V" "Stratix IV" \
"Cyclone IV GX" "Cyclone IV E" "Cyclone III GL" "Arria II GZ" "Arria II GX"}
proc check_device_ini {device_families_list} {
set enable_max10 [get_quartus_ini enable_max10_active_serial ENABLED]
if {$enable_max10 == 1} {
lappend device_families_list "MAX 10 FPGA"
}
return $device_families_list
}
set device_list [check_device_ini $all_supported_device_families_list]
set_module_property SUPPORTED_DEVICE_FAMILIES $device_list
add_parameter DEVICE_FAMILY STRING
set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
set_parameter_property DEVICE_FAMILY VISIBLE false
set_parameter_property DEVICE_FAMILY HDL_PARAMETER true
add_parameter ASI_WIDTH INTEGER 1
set_parameter_property ASI_WIDTH DEFAULT_VALUE 1
set_parameter_property ASI_WIDTH DISPLAY_NAME ASI_WIDTH
set_parameter_property ASI_WIDTH DERIVED true
set_parameter_property ASI_WIDTH TYPE INTEGER
set_parameter_property ASI_WIDTH VISIBLE false
set_parameter_property ASI_WIDTH UNITS None
set_parameter_property ASI_WIDTH ALLOWED_RANGES {1, 4}
set_parameter_property ASI_WIDTH HDL_PARAMETER true
add_parameter CS_WIDTH INTEGER 1
set_parameter_property CS_WIDTH DEFAULT_VALUE 1
set_parameter_property CS_WIDTH DISPLAY_NAME CS_WIDTH
set_parameter_property CS_WIDTH DERIVED true
set_parameter_property CS_WIDTH TYPE INTEGER
set_parameter_property CS_WIDTH VISIBLE false
set_parameter_property CS_WIDTH UNITS None
set_parameter_property CS_WIDTH ALLOWED_RANGES {1, 3}
set_parameter_property CS_WIDTH HDL_PARAMETER true
add_parameter ADDR_WIDTH INTEGER 19
set_parameter_property ADDR_WIDTH DEFAULT_VALUE 19
set_parameter_property ADDR_WIDTH DISPLAY_NAME ADDR_WIDTH
set_parameter_property ADDR_WIDTH DERIVED true
set_parameter_property ADDR_WIDTH TYPE INTEGER
set_parameter_property ADDR_WIDTH VISIBLE false
set_parameter_property ADDR_WIDTH UNITS None
# 16M-19bit, 32M-20bit, 64M-21bit, 128M-22bit, 256M-23bit, 512M-24bit, 1024M-25bit, 2048M-26bit...
set_parameter_property ADDR_WIDTH ALLOWED_RANGES {19, 20, 21, 22, 23, 24, 25, 26, 27, 28}
set_parameter_property ADDR_WIDTH HDL_PARAMETER true
add_parameter ASMI_ADDR_WIDTH INTEGER 24
set_parameter_property ASMI_ADDR_WIDTH DEFAULT_VALUE 24
set_parameter_property ASMI_ADDR_WIDTH DISPLAY_NAME ASMI_ADDR_WIDTH
set_parameter_property ASMI_ADDR_WIDTH DERIVED true
set_parameter_property ASMI_ADDR_WIDTH TYPE INTEGER
set_parameter_property ASMI_ADDR_WIDTH VISIBLE false
set_parameter_property ASMI_ADDR_WIDTH UNITS None
set_parameter_property ASMI_ADDR_WIDTH ALLOWED_RANGES {24, 32}
set_parameter_property ASMI_ADDR_WIDTH HDL_PARAMETER true
add_parameter ENABLE_4BYTE_ADDR INTEGER "0"
set_parameter_property ENABLE_4BYTE_ADDR DISPLAY_NAME "Enable 4-byte addressing mode"
set_parameter_property ENABLE_4BYTE_ADDR DESCRIPTION "Check to enable 4-byte addressing mode for device larger than 128Mbyte"
set_parameter_property ENABLE_4BYTE_ADDR AFFECTS_GENERATION true
set_parameter_property ENABLE_4BYTE_ADDR VISIBLE false
set_parameter_property ENABLE_4BYTE_ADDR HDL_PARAMETER true
set_parameter_property ENABLE_4BYTE_ADDR DERIVED true
# +-----------------------------------
# add system info parameter
add_parameter deviceFeaturesSystemInfo STRING "None"
set_parameter_property deviceFeaturesSystemInfo system_info "DEVICE_FEATURES"
set_parameter_property deviceFeaturesSystemInfo VISIBLE false
add_parameter DDASI INTEGER "0"
set_parameter_property DDASI DISPLAY_NAME "Disable dedicated Active Serial interface"
set_parameter_property DDASI DESCRIPTION "Check to route ASMIBLOCK signals to top level of design"
set_parameter_property DDASI AFFECTS_GENERATION true
set_parameter_property DDASI VISIBLE false
set_parameter_property DDASI DERIVED false
add_parameter clkFreq LONG
set_parameter_property clkFreq DEFAULT_VALUE {0}
set_parameter_property clkFreq DISPLAY_NAME {clkFreq}
set_parameter_property clkFreq VISIBLE {0}
set_parameter_property clkFreq AFFECTS_GENERATION {1}
set_parameter_property clkFreq HDL_PARAMETER {0}
set_parameter_property clkFreq SYSTEM_INFO {clock_rate clk}
set_parameter_property clkFreq SYSTEM_INFO_TYPE {CLOCK_RATE}
set_parameter_property clkFreq SYSTEM_INFO_ARG {clock_sink}
#
# connection point clock_sink
#
add_interface clock_sink clock end
set_interface_property clock_sink clockRate 0
set_interface_property clock_sink ENABLED true
set_interface_property clock_sink EXPORT_OF ""
set_interface_property clock_sink PORT_NAME_MAP ""
set_interface_property clock_sink CMSIS_SVD_VARIABLES ""
set_interface_property clock_sink SVD_ADDRESS_GROUP ""
add_interface_port clock_sink clk clk Input 1
#
# connection point reset
#
add_interface reset reset end
set_interface_property reset associatedClock clock_sink
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""
add_interface_port reset reset_n reset_n Input 1
#
# connection point avl_csr
#
add_interface avl_csr avalon end
set_interface_property avl_csr addressUnits WORDS
set_interface_property avl_csr associatedClock clock_sink
set_interface_property avl_csr associatedReset reset
set_interface_property avl_csr bitsPerSymbol 8
set_interface_property avl_csr burstOnBurstBoundariesOnly false
set_interface_property avl_csr burstcountUnits WORDS
set_interface_property avl_csr explicitAddressSpan 0
set_interface_property avl_csr holdTime 0
set_interface_property avl_csr linewrapBursts false
set_interface_property avl_csr maximumPendingReadTransactions 1
set_interface_property avl_csr maximumPendingWriteTransactions 0
set_interface_property avl_csr readLatency 0
set_interface_property avl_csr readWaitTime 0
set_interface_property avl_csr setupTime 0
set_interface_property avl_csr timingUnits Cycles
set_interface_property avl_csr writeWaitTime 0
set_interface_property avl_csr ENABLED true
set_interface_property avl_csr EXPORT_OF ""
set_interface_property avl_csr PORT_NAME_MAP ""
set_interface_property avl_csr CMSIS_SVD_VARIABLES ""
set_interface_property avl_csr SVD_ADDRESS_GROUP ""
add_interface_port avl_csr avl_csr_read read Input 1
add_interface_port avl_csr avl_csr_waitrequest waitrequest Output 1
add_interface_port avl_csr avl_csr_write write Input 1
add_interface_port avl_csr avl_csr_addr address Input 3
add_interface_port avl_csr avl_csr_wrdata writedata Input 32
add_interface_port avl_csr avl_csr_rddata readdata Output 32
add_interface_port avl_csr avl_csr_rddata_valid readdatavalid Output 1
#
# connection point avl_mem
#
add_interface avl_mem avalon end
set_interface_property avl_mem addressUnits WORDS
set_interface_property avl_mem associatedClock clock_sink
set_interface_property avl_mem associatedReset reset
set_interface_property avl_mem bitsPerSymbol 8
set_interface_property avl_mem burstOnBurstBoundariesOnly false
set_interface_property avl_mem burstcountUnits WORDS
set_interface_property avl_mem explicitAddressSpan 0
set_interface_property avl_mem holdTime 0
set_interface_property avl_mem linewrapBursts true
set_interface_property avl_mem maximumPendingReadTransactions 1
set_interface_property avl_mem maximumPendingWriteTransactions 0
set_interface_property avl_mem constantBurstBehavior true
set_interface_property avl_mem readLatency 0
set_interface_property avl_mem readWaitTime 0
set_interface_property avl_mem setupTime 0
set_interface_property avl_mem timingUnits Cycles
set_interface_property avl_mem writeWaitTime 0
set_interface_property avl_mem ENABLED true
set_interface_property avl_mem EXPORT_OF ""
set_interface_property avl_mem PORT_NAME_MAP ""
set_interface_property avl_mem CMSIS_SVD_VARIABLES ""
set_interface_property avl_mem SVD_ADDRESS_GROUP ""
add_interface_port avl_mem avl_mem_write write Input 1
add_interface_port avl_mem avl_mem_burstcount burstcount Input 7
add_interface_port avl_mem avl_mem_waitrequest waitrequest Output 1
add_interface_port avl_mem avl_mem_read read Input 1
add_interface_port avl_mem avl_mem_addr address Input ADDR_WIDTH
add_interface_port avl_mem avl_mem_wrdata writedata Input 32
add_interface_port avl_mem avl_mem_rddata readdata Output 32
add_interface_port avl_mem avl_mem_rddata_valid readdatavalid Output 1
add_interface_port avl_mem avl_mem_byteenable byteenable Input 4
#
# connection point interrupt_sender
#
add_interface interrupt_sender interrupt end
set_interface_property interrupt_sender associatedAddressablePoint avl_csr
set_interface_property interrupt_sender associatedClock clock_sink
set_interface_property interrupt_sender associatedReset reset
set_interface_property interrupt_sender bridgedReceiverOffset ""
set_interface_property interrupt_sender bridgesToReceiver ""
set_interface_property interrupt_sender ENABLED true
set_interface_property interrupt_sender EXPORT_OF ""
set_interface_property interrupt_sender PORT_NAME_MAP ""
set_interface_property interrupt_sender CMSIS_SVD_VARIABLES ""
set_interface_property interrupt_sender SVD_ADDRESS_GROUP ""
add_interface_port interrupt_sender irq irq Output 1
proc proc_get_derive_addr_width {flash_type} {
switch $flash_type {
"EPCS16" - "EPCQ16" {
return 19
}
"EPCS64" - "EPCQ64" {
return 21
}
"EPCS128" - "EPCQ128" {
return 22
}
"EPCQ32" {
return 20
}
"EPCQ256" - "EPCQL256" {
return 23
}
"EPCQ512" - "EPCQL512" {
return 24
}
"EPCQL1024" {
return 25
}
default {
# Should never enter this function
send_message error "$flash_type is not a valid flash type"
}
}
}
set all_supported_SPI_list {"EPCS16" "EPCS64" "EPCS128" "EPCQ16" "EPCQ32" "EPCQ64" "EPCQ128" "EPCQ256" \
"EPCQ512" "EPCQL256" "EPCQL512" "EPCQL1024"}
# SPI device selection
add_parameter FLASH_TYPE STRING "EPCQ16"
set_parameter_property FLASH_TYPE DISPLAY_NAME "Configuration device type"
set_parameter_property FLASH_TYPE ALLOWED_RANGES $all_supported_SPI_list
set_parameter_property FLASH_TYPE DESCRIPTION "Select targeted EPCS/EPCQ devices"
set_parameter_property FLASH_TYPE AFFECTS_GENERATION true
set_parameter_property FLASH_TYPE VISIBLE true
set_parameter_property FLASH_TYPE DERIVED false
add_parameter IO_MODE STRING "STANDARD"
set_parameter_property IO_MODE DISPLAY_NAME "Choose I/O mode"
set_parameter_property IO_MODE ALLOWED_RANGES {"STANDARD" "QUAD"}
set_parameter_property IO_MODE DESCRIPTION "Select extended data width when Fast Read operation is enabled"
add_parameter CHIP_SELS INTEGER "1"
set_parameter_property CHIP_SELS DISPLAY_NAME "Number of Chip Selects used"
set_parameter_property CHIP_SELS ALLOWED_RANGES {1 2 3}
set_parameter_property CHIP_SELS DESCRIPTION "Number of EPCQ(L) devices that are attached and need a CHIPSEL"
set_parameter_property CHIP_SELS HDL_PARAMETER true
set_parameter_property CHIP_SELS AFFECTS_GENERATION true
#
# Add instance
#
proc add_topwrapper_fileset_proc {altera_epcq_controller} {
# QSPI that supported for 4-byte addressing - en4b_addr, ex4b_addr
set supported_4byte_addr {"EPCQ256" "EPCQ512" "EPCQL256" "EPCQL512" "EPCQL1024" "N25Q512"}
set DDASI [ get_parameter_value DDASI ]
set DEVICE_FAMILY [ get_parameter_value DEVICE_FAMILY ]
set FLASH_TYPE [ get_parameter_value FLASH_TYPE ]
set ADDR_WIDTH [ get_parameter_value ADDR_WIDTH ]
set is_4byte_addr_support "false"
# check whether devices supporting multiple flash - only for Arria 10
if {[check_device_family_equivalence $DEVICE_FAMILY "Arria 10"]} {
set MULTICHIP 1
} else {
set MULTICHIP 0
}
if { $DDASI eq "1" } {
set DDASI_ON 1
} else {
set DDASI_ON 0
}
if { $FLASH_TYPE eq "EPCS16" || $FLASH_TYPE eq "EPCS64" } {
set ENABLE_SID 1
} else {
set ENABLE_SID 0
}
if { $FLASH_TYPE eq "EPCQL512" || $FLASH_TYPE eq "EPCQL1024" } {
set ENABLE_BULK_ERASE 0
} else {
set ENABLE_BULK_ERASE 1
}
# check whether SPI device support 4-byte addressing
foreach re_spi_1 $supported_4byte_addr {
if {$re_spi_1 eq $FLASH_TYPE} {
set is_4byte_addr_support "true"
break;
}
}
if {$is_4byte_addr_support eq "true"} {
set ENABLE_4BYTE_ADDR_CODE 1
} else {
set ENABLE_4BYTE_ADDR_CODE 0
}
# ---------------------------------
# Terp for top level wrapper
# ---------------------------------
#Do Terp
set template_file [ file join "./" "altera_epcq_controller_wrapper.sv.terp" ]
set template [ read [ open $template_file r ] ]
if {$DDASI_ON} {
set params(DDASI_ON) "`define DDASI_ON"
} else {
set params(DDASI_ON) ""
}
if {$MULTICHIP} {
set params(MULTICHIP) "`define MULTICHIP"
} else {
set params(MULTICHIP) ""
}
if {$ENABLE_SID} {
set params(SID_EN) "`define ENABLE_SID"
} else {
set params(SID_EN) ""
}
if {$ENABLE_BULK_ERASE} {
set params(BULK_ERASE_EN) "`define ENABLE_BULK_ERASE"
} else {
set params(BULK_ERASE_EN) ""
}
if {$ENABLE_4BYTE_ADDR_CODE} {
set params(4BYTE_ADDR_EN) "`define ENABLE_4BYTE_ADDR_CODE"
} else {
set params(4BYTE_ADDR_EN) ""
}
set result [ altera_terp $template params ]
#Add top wrapper file
add_fileset_file ./altera_epcq_controller_wrapper.sv SYSTEM_VERILOG TEXT $result
}
# This proc is called by elaboration proc to set embeddedsw C Macros assignments
# used by downstream tools
proc set_cmacros {is_qspi flash_type} {
if {$is_qspi eq "true"} {
set_module_assignment embeddedsw.CMacro.IS_EPCS 0
} else {
set_module_assignment embeddedsw.CMacro.IS_EPCS 1
}
#string name of flash
set_module_assignment embeddedsw.CMacro.FLASH_TYPE $flash_type
#page size in bytes
set_module_assignment embeddedsw.CMacro.PAGE_SIZE 256
#sector and subsector size in bytes
set_module_assignment embeddedsw.CMacro.SUBSECTOR_SIZE 4096
set_module_assignment embeddedsw.CMacro.SECTOR_SIZE 65536
#set number of sectors
switch $flash_type {
"EPCS16" - "EPCQ16" {
set_module_assignment embeddedsw.CMacro.NUMBER_OF_SECTORS 32
}
"EPCQ32" {
set_module_assignment embeddedsw.CMacro.NUMBER_OF_SECTORS 64
}
"EPCS64" - "EPCQ64" {
set_module_assignment embeddedsw.CMacro.NUMBER_OF_SECTORS 128
}
"EPCS128" - "EPCQ128" {
set_module_assignment embeddedsw.CMacro.NUMBER_OF_SECTORS 256
}
"EPCQ256" - "EPCQL256" {
set_module_assignment embeddedsw.CMacro.NUMBER_OF_SECTORS 512
}
"EPCQ512" - "EPCQL512" {
set_module_assignment embeddedsw.CMacro.NUMBER_OF_SECTORS 1024
}
"EPCQL1024" {
set_module_assignment embeddedsw.CMacro.NUMBER_OF_SECTORS 2048
}
default {
# Should never enter this function
send_message error "$flash_type is not a valid flash type"
}
}
}
proc elaboration {} {
# QSPI that supported for 4-byte addressing - en4b_addr, ex4b_addr
set supported_4byte_addr {"EPCQ256" "EPCQ512" "EPCQL256" "EPCQL512" "EPCQL1024" "N25Q512"}
set DDASI_ON [ get_parameter_value DDASI ]
set FLASH_TYPE [ get_parameter_value FLASH_TYPE ]
set IO_MODE [ get_parameter_value IO_MODE ]
set DEVICE_FAMILY [ get_parameter_value DEVICE_FAMILY ]
set ASI_WIDTH [ get_parameter_value ASI_WIDTH ]
set CS_WIDTH [ get_parameter_value CS_WIDTH ]
set ASMI_ADDR_WIDTH [ get_parameter_value ASMI_ADDR_WIDTH ]
set CHIP_SELS [ get_parameter_value CHIP_SELS]
set temp_addr_width [ proc_get_derive_addr_width [ get_parameter_value FLASH_TYPE ] ]
set clkFreq [ get_parameter_value clkFreq ]
set is_4byte_addr_support "false"
set is_qspi "false"
# we're not using slow and expensive EPCS flash, thus higher frequency allowed
if { $clkFreq > 50000000 } {
send_message error "The maximum input clock frequency for Altera Serial Flash controller is 25Mhz."
}
# check whether SPI device support 4-byte addressing
foreach re_spi_1 $supported_4byte_addr {
if {$re_spi_1 eq $FLASH_TYPE} {
set is_4byte_addr_support "true"
break;
}
}
if {$is_4byte_addr_support eq "true"} {
set_parameter_value ENABLE_4BYTE_ADDR "1"
set_parameter_value ASMI_ADDR_WIDTH 32
} else {
set_parameter_value ENABLE_4BYTE_ADDR "0"
set_parameter_value ASMI_ADDR_WIDTH 24
}
# check whether devices supporting multiple flash - only for Arria 10
if {[check_device_family_equivalence $DEVICE_FAMILY "Arria 10"]} {
set is_multi_flash_support "true"
if {$CHIP_SELS eq 3 } {set_parameter_value ADDR_WIDTH [ expr $temp_addr_width + 2]}
if {$CHIP_SELS eq 2 } {set_parameter_value ADDR_WIDTH [ expr $temp_addr_width + 1]}
if {$CHIP_SELS eq 1 } {set_parameter_value ADDR_WIDTH $temp_addr_width }
} else {
set is_multi_flash_support "false"
set_parameter_value ADDR_WIDTH $temp_addr_width
}
set_instance_parameter_value altera_epcq_controller_core DDASI $DDASI_ON
set_instance_parameter_value altera_epcq_controller_core FLASH_TYPE $FLASH_TYPE
set_instance_parameter_value altera_epcq_controller_core IO_MODE $IO_MODE
set_instance_parameter_value altera_epcq_controller_core ASI_WIDTH $ASI_WIDTH
set_instance_parameter_value altera_epcq_controller_core CS_WIDTH $CS_WIDTH
set_instance_parameter_value altera_epcq_controller_core CHIP_SELS $CHIP_SELS
set_instance_parameter_value altera_epcq_controller_core ASMI_ADDR_WIDTH [ get_parameter_value ASMI_ADDR_WIDTH ]
set_instance_parameter_value altera_epcq_controller_core ADDR_WIDTH [ get_parameter_value ADDR_WIDTH ]
set_instance_parameter_value altera_epcq_controller_core ENABLE_4BYTE_ADDR [ get_parameter_value ENABLE_4BYTE_ADDR ]
set QSPI_list {"EPCQ16" "EPCQ32" "EPCQ64" "EPCQ128" "EPCQ256" "EPCQ512" "EPCQL256" "EPCQL512" "EPCQL1024" \
"N25Q512" "S25FL127S"}
# devices that supported QSPI - Quad/Dual data width, asmi_dataout, asmi_sdoin, asmi_dataoe
set supported_QSPI_devices_list {"Arria 10" "Cyclone V" "Arria V GZ" "Arria V" "Stratix V"}
# devices that supported simulation
set supported_sim_devices_list {"Arria 10" "Cyclone V" "Arria V GZ" "Arria V" "Stratix V" "MAX 10 FPGA"}
# check whether is QSPI devices
foreach re_spi_0 $QSPI_list {
if {$re_spi_0 eq $FLASH_TYPE} {
set is_qspi "true"
break;
}
}
if {[check_device_family_equivalence $DEVICE_FAMILY $supported_QSPI_devices_list]} {
set is_qspi_devices_list "true"
} else {
set is_qspi_devices_list "false"
}
if {[check_device_family_equivalence $DEVICE_FAMILY $supported_sim_devices_list]} {
set is_sim_devices_list "true"
} else {
set is_sim_devices_list "false"
}
if {$is_qspi_devices_list eq "true" && $is_qspi eq "true"} {
set_parameter_property IO_MODE ENABLED true
set_instance_parameter_value altera_asmi_parallel DATA_WIDTH $IO_MODE
set_parameter_value ASI_WIDTH 4
} else {
set_parameter_property IO_MODE ENABLED false
set_parameter_value ASI_WIDTH 1
}
if { $FLASH_TYPE eq "EPCQL512" || $FLASH_TYPE eq "EPCQL1024" } {
set_instance_parameter_value altera_asmi_parallel gui_bulk_erase false
set ENABLE_BULK_ERASE 0
} else {
set_instance_parameter_value altera_asmi_parallel gui_bulk_erase true
set ENABLE_BULK_ERASE 1
}
if { $is_multi_flash_support eq "true"} {
set_parameter_value CS_WIDTH 3
set_parameter_property CHIP_SELS ENABLED true
} else {
set_parameter_value CS_WIDTH 1
set_parameter_property CHIP_SELS ENABLED false
}
set_instance_parameter_value altera_asmi_parallel EPCS_TYPE $FLASH_TYPE
set_instance_parameter_value altera_asmi_parallel gui_fast_read true
set_instance_parameter_value altera_asmi_parallel gui_page_write true
if { $FLASH_TYPE eq "EPCS16" || $FLASH_TYPE eq "EPCS64" } {
set_instance_parameter_value altera_asmi_parallel gui_read_sid true
} else {
set_instance_parameter_value altera_asmi_parallel gui_read_sid false
}
set_instance_parameter_value altera_asmi_parallel gui_read_rdid true
set_instance_parameter_value altera_asmi_parallel gui_read_status true
set_instance_parameter_value altera_asmi_parallel gui_sector_erase true
set_instance_parameter_value altera_asmi_parallel gui_sector_protect true
set_instance_parameter_value altera_asmi_parallel gui_wren true
set_instance_parameter_value altera_asmi_parallel gui_write true
set_instance_parameter_value altera_asmi_parallel gui_read_dummyclk true
set_instance_parameter_value altera_asmi_parallel PAGE_SIZE 256
set_instance_parameter_value altera_asmi_parallel gui_use_asmiblock $DDASI_ON
if {$is_sim_devices_list eq "true"} {
set_instance_parameter_value altera_asmi_parallel ENABLE_SIM true
} else {
set_instance_parameter_value altera_asmi_parallel ENABLE_SIM false
}
set_cmacros $is_qspi $FLASH_TYPE
}
# add ASMI PARALLEL
add_hdl_instance altera_asmi_parallel altera_asmi_parallel
# add EPCQ CONTROLLER
add_hdl_instance altera_epcq_controller_core altera_epcq_controller_core
# +-------------------------------------
# | Add settings needed by Nios tools
# +-------------------------------------
# Tells us component is a flash
set_module_assignment embeddedsw.memoryInfo.IS_FLASH 1
# interface assignments for embedded software
set_interface_assignment avl_mem embeddedsw.configuration.isFlash 1
set_interface_assignment avl_mem embeddedsw.configuration.isMemoryDevice 1
set_interface_assignment avl_mem embeddedsw.configuration.isNonVolatileStorage 1
set_interface_assignment avl_mem embeddedsw.configuration.isPrintableDevice 0
# These assignments tells tools to create byte-addressed .hex files only
set_module_assignment embeddedsw.memoryInfo.GENERATE_HEX 1
set_module_assignment embeddedsw.memoryInfo.USE_BYTE_ADDRESSING_FOR_HEX 1
set_module_assignment embeddedsw.memoryInfo.GENERATE_DAT_SYM 0
set_module_assignment embeddedsw.memoryInfo.GENERATE_FLASH 0
# Width of memory
set_module_assignment embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH 32
# Output directories for programming files
#set_module_assignment embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR {SIM_DIR}
#set_module_assignment embeddedsw.memoryInfo.FLASH_INSTALL_DIR {APP_DIR}
set_module_assignment embeddedsw.memoryInfo.HEX_INSTALL_DIR {QPF_DIR}
# Module assignments related to names of simulation files
#set_module_assignment postgeneration.simulation.init_file.param_name {INIT_FILENAME}
#set_module_assignment postgeneration.simulation.init_file.type {MEM_INIT}
# +-------------------------------------
# | Add settings needed by DTG tools
# +-------------------------------------
# add device tree properties
set_module_assignment embeddedsw.dts.vendor "altr"
set_module_assignment embeddedsw.dts.name "epcq"
set_module_assignment embeddedsw.dts.group "epcq"
set_module_assignment embeddedsw.dts.compatible "altr,epcq-1.0"
## Add documentation links for user guide and/or release notes
add_documentation_link "User Guide" https://documentation.altera.com/#/link/sfo1400787952932/iga1431459459085
add_documentation_link "Release Notes" https://documentation.altera.com/#/link/hco1421698042087/hco1421697689300

2
ossc.qsf
View File

@ -218,7 +218,7 @@ set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/ossc_la.stp
set_global_assignment -name FITTER_EFFORT "AUTO FIT"
set_global_assignment -name SEED 6
set_global_assignment -name SEED 2

6
ossc_sw_bsp.project
View File

@ -39,6 +39,8 @@
<VirtualDirectory Name="sys_controller_bsp">
<VirtualDirectory Name="drivers">
<VirtualDirectory Name="inc">
<File Name="software/sys_controller_bsp/drivers/inc/altera_epcq_controller2_regs.h"/>
<File Name="software/sys_controller_bsp/drivers/inc/altera_epcq_controller2.h"/>
<File Name="software/sys_controller_bsp/drivers/inc/pll_reconfig_regs.h"/>
<File Name="software/sys_controller_bsp/drivers/inc/osd_generator_regs.h"/>
<File Name="software/sys_controller_bsp/drivers/inc/sc_config_regs.h"/>
@ -48,19 +50,17 @@
<File Name="software/sys_controller_bsp/drivers/inc/altera_avalon_jtag_uart_regs.h"/>
<File Name="software/sys_controller_bsp/drivers/inc/ci_crc.h"/>
<File Name="software/sys_controller_bsp/drivers/inc/crc.h"/>
<File Name="software/sys_controller_bsp/drivers/inc/altera_epcq_controller_mod_regs.h"/>
<File Name="software/sys_controller_bsp/drivers/inc/altera_avalon_jtag_uart_fd.h"/>
<File Name="software/sys_controller_bsp/drivers/inc/altera_epcq_controller_mod.h"/>
<File Name="software/sys_controller_bsp/drivers/inc/i2c_opencores_regs.h"/>
<File Name="software/sys_controller_bsp/drivers/inc/i2c_opencores.h"/>
<File Name="software/sys_controller_bsp/drivers/inc/Altera_UP_SD_Card_Avalon_Interface_mod.h"/>
<File Name="software/sys_controller_bsp/drivers/inc/altera_avalon_pio_regs.h"/>
</VirtualDirectory>
<VirtualDirectory Name="src">
<File Name="software/sys_controller_bsp/drivers/src/altera_epcq_controller2.c"/>
<File Name="software/sys_controller_bsp/drivers/src/altera_avalon_timer_vars.c"/>
<File Name="software/sys_controller_bsp/drivers/src/altera_avalon_timer_ts.c"/>
<File Name="software/sys_controller_bsp/drivers/src/altera_avalon_timer_sc.c"/>
<File Name="software/sys_controller_bsp/drivers/src/altera_epcq_controller_mod.c"/>
<File Name="software/sys_controller_bsp/drivers/src/altera_avalon_jtag_uart_read.c"/>
<File Name="software/sys_controller_bsp/drivers/src/altera_avalon_jtag_uart_ioctl.c"/>
<File Name="software/sys_controller_bsp/drivers/src/ci_crc.c"/>

6
software/ossc_sw.project
View File

@ -31,9 +31,9 @@
<Excludepaths/>
<Ignorefiles/>
<Extensions>
<![CDATA[cpp;c;h;hpp;xrc;wxcp;fbp]]>
<![CDATA[*.cpp;*.c;*.h;*.hpp;*.xrc;*.wxcp;*.fbp]]>
</Extensions>
<Topleveldir>../software</Topleveldir>
<Topleveldir>/home/markus/Code/ossc/software</Topleveldir>
</Reconciliation>
<VirtualDirectory Name="sys_controller">
<VirtualDirectory Name="ths7353">
@ -74,6 +74,8 @@
<File Name="sys_controller/memory/sdcard.c"/>
</VirtualDirectory>
<VirtualDirectory Name="ossc">
<File Name="sys_controller/ossc/utils.h"/>
<File Name="sys_controller/ossc/utils.c"/>
<File Name="sys_controller/ossc/menu.c"/>
<File Name="sys_controller/ossc/menu.h"/>
<File Name="sys_controller/ossc/sysconfig.h"/>

17051
software/sys_controller/mem_init/sys_onchip_memory2_0.hex
View File

File diff suppressed because it is too large Load Diff

8
software/sys_controller/memory/flash.c
View File

@ -35,7 +35,7 @@ int init_flash()
extern alt_llist alt_flash_dev_list;
epcq_dev = (alt_flash_dev*)alt_flash_dev_list.next;
#else
epcq_dev = alt_flash_open_dev(EPCQ_CONTROLLER_0_AVL_MEM_NAME);
epcq_dev = alt_flash_open_dev(EPCQ_CONTROLLER2_0_AVL_MEM_NAME);
#endif
if (epcq_dev == NULL)
@ -46,14 +46,16 @@ int init_flash()
int verify_flash(alt_u32 offset, alt_u32 length, alt_u32 golden_crc, alt_u8 *tmpbuf)
{
alt_u32 crcval=0, i, bytes_to_read;
alt_u32 crcval=0, i, j, bytes_to_read;
int retval;
for (i=0; i<length; i=i+PAGESIZE) {
bytes_to_read = ((length-i < PAGESIZE) ? (length-i) : PAGESIZE);
//retval = read_flash(i, bytes_to_read, tmpbuf);
retval = alt_epcq_controller_read(epcq_dev, offset+i, tmpbuf, bytes_to_read);
retval = alt_epcq_controller2_read(epcq_dev, offset+i, tmpbuf, bytes_to_read);
for (j=0; j<bytes_to_read; j++)
tmpbuf[j] = bitswap8(tmpbuf[j]);
if (retval != 0)
return retval;

2
software/sys_controller/memory/flash.h
View File

@ -22,7 +22,7 @@
#include "alt_types.h"
#include "sysconfig.h"
#include "altera_epcq_controller_mod.h"
#include "altera_epcq_controller2.h"
// EPCS16 pagesize is 256 bytes
// Flash is split 50-50 to FW and userdata, 1MB each

16
software/sys_controller/memory/sdcard.c
View File

@ -21,7 +21,7 @@
#include <string.h>
#include "sdcard.h"
#include "flash.h"
#include "lcd.h"
#include "utils.h"
extern alt_flash_dev *epcq_dev;
@ -42,7 +42,7 @@ int check_sdcard(alt_u8 *databuf)
int copy_sd_to_flash(alt_u32 sd_blknum, alt_u32 flash_pagenum, alt_u32 length, alt_u8 *tmpbuf)
{
SDRESULTS res;
int retval;
int retval, i;
alt_u32 bytes_to_rw;
while (length > 0) {
@ -54,12 +54,14 @@ int copy_sd_to_flash(alt_u32 sd_blknum, alt_u32 flash_pagenum, alt_u32 length, a
}
if ((flash_pagenum % PAGES_PER_SECTOR) == 0) {
retval = alt_epcq_controller_erase_block(epcq_dev, flash_pagenum*PAGESIZE);
retval = alt_epcq_controller2_erase_block(epcq_dev, flash_pagenum*PAGESIZE);
if (retval != 0)
return retval;
}
retval = alt_epcq_controller_write_block(epcq_dev, ((flash_pagenum/PAGES_PER_SECTOR)*SECTORSIZE), flash_pagenum*PAGESIZE, tmpbuf, bytes_to_rw);
for (i=0; i<bytes_to_rw; i++)
tmpbuf[i] = bitswap8(tmpbuf[i]);
retval = alt_epcq_controller2_write_block(epcq_dev, ((flash_pagenum/PAGES_PER_SECTOR)*SECTORSIZE), flash_pagenum*PAGESIZE, tmpbuf, bytes_to_rw);
if (retval != 0)
return retval;
@ -74,12 +76,14 @@ int copy_sd_to_flash(alt_u32 sd_blknum, alt_u32 flash_pagenum, alt_u32 length, a
int copy_flash_to_sd(alt_u32 flash_pagenum, alt_u32 sd_blknum, alt_u32 length, alt_u8 *tmpbuf)
{
SDRESULTS res;
int retval;
int retval, i;
alt_u32 bytes_to_rw;
while (length > 0) {
bytes_to_rw = (length < SD_BLK_SIZE) ? length : SD_BLK_SIZE;
retval = alt_epcq_controller_read(epcq_dev, flash_pagenum*PAGESIZE, tmpbuf, bytes_to_rw);
retval = alt_epcq_controller2_read(epcq_dev, flash_pagenum*PAGESIZE, tmpbuf, bytes_to_rw);
for (i=0; i<bytes_to_rw; i++)
tmpbuf[i] = bitswap8(tmpbuf[i]);
if (retval != 0)
return retval;

2
software/sys_controller/ossc/firmware.h
View File

@ -24,7 +24,7 @@
#include "sysconfig.h"
#define FW_VER_MAJOR 0
#define FW_VER_MINOR 88
#define FW_VER_MINOR 89
#define PROFILE_VER_MAJOR 0
#define PROFILE_VER_MINOR 88

33
software/sys_controller/ossc/userdata.c
View File

@ -28,6 +28,7 @@
#include "controls.h"
#include "av_controller.h"
#include "menu.h"
#include "utils.h"
#include "altera_avalon_pio_regs.h"
extern alt_u16 rc_keymap[REMOTE_MAX_KEYS];
@ -55,7 +56,7 @@ int write_userdata(alt_u8 entry)
alt_u16 pageoffset, srcoffset;
alt_u8 pageno;
alt_u32 bytes_to_w;
int retval;
int retval, i;
if (entry > MAX_USERDATA_ENTRY) {
printf("invalid entry\n");
@ -82,7 +83,9 @@ int write_userdata(alt_u8 entry)
((ude_initcfg*)databuf)->osd_enable = osd_enable_pre;
((ude_initcfg*)databuf)->osd_status_timeout = osd_status_timeout_pre;
memcpy(((ude_initcfg*)databuf)->keys, rc_keymap, sizeof(rc_keymap));
retval = alt_epcq_controller_write(epcq_dev, (USERDATA_OFFSET+entry*SECTORSIZE), databuf, sizeof(ude_initcfg));
for (i=0; i<sizeof(ude_initcfg); i++)
databuf[i] = bitswap8(databuf[i]);
retval = alt_epcq_controller2_write(epcq_dev, (USERDATA_OFFSET+entry*SECTORSIZE), databuf, sizeof(ude_initcfg));
if (retval != 0)
return retval;
@ -110,15 +113,25 @@ int write_userdata(alt_u8 entry)
memcpy(databuf+pageoffset, (char*)video_modes, PAGESIZE-pageoffset);
srcoffset = PAGESIZE-pageoffset;
vm_to_write -= PAGESIZE-pageoffset;
retval = alt_epcq_controller_write(epcq_dev, (USERDATA_OFFSET+entry*SECTORSIZE), databuf, PAGESIZE);
for (i=0; i<PAGESIZE; i++)
databuf[i] = bitswap8(databuf[i]);
retval = alt_epcq_controller2_write(epcq_dev, (USERDATA_OFFSET+entry*SECTORSIZE), databuf, PAGESIZE);
if (retval != 0)
return retval;
// then write the rest
if (vm_to_write > 0) {
retval = alt_epcq_controller_write_block(epcq_dev, (USERDATA_OFFSET+entry*SECTORSIZE), (USERDATA_OFFSET+entry*SECTORSIZE+PAGESIZE), (alt_u8*)video_modes+srcoffset, vm_to_write);
// then write the rest page by page
pageno = 1;
while (vm_to_write > 0) {
memcpy(databuf, (char*)video_modes+srcoffset, (vm_to_write > PAGESIZE) ? PAGESIZE : vm_to_write);
for (i=0; i<PAGESIZE; i++)
databuf[i] = bitswap8(databuf[i]);
retval = alt_epcq_controller2_write_block(epcq_dev, (USERDATA_OFFSET+entry*SECTORSIZE), (USERDATA_OFFSET+entry*SECTORSIZE+pageno*PAGESIZE), databuf, (vm_to_write > PAGESIZE) ? PAGESIZE : vm_to_write);
if (retval != 0)
return retval;
srcoffset += PAGESIZE;
vm_to_write = (vm_to_write < PAGESIZE) ? 0 : (vm_to_write - PAGESIZE);
pageno++;
}
printf("Profile %u data written (%u bytes)\n", entry, sizeof(avconfig_t)+VIDEO_MODES_SIZE);
@ -145,7 +158,9 @@ int read_userdata(alt_u8 entry, int dry_run)
return -1;
}
retval = alt_epcq_controller_read(epcq_dev, (USERDATA_OFFSET+entry*SECTORSIZE), databuf, PAGESIZE);
retval = alt_epcq_controller2_read(epcq_dev, (USERDATA_OFFSET+entry*SECTORSIZE), databuf, PAGESIZE);
for (i=0; i<PAGESIZE; i++)
databuf[i] = bitswap8(databuf[i]);
if (retval != 0)
return retval;
@ -213,7 +228,9 @@ int read_userdata(alt_u8 entry, int dry_run)
pageoffset = 0;
pageno++;
// check
retval = alt_epcq_controller_read(epcq_dev, (USERDATA_OFFSET+entry*SECTORSIZE+pageno*PAGESIZE), databuf, PAGESIZE);
retval = alt_epcq_controller2_read(epcq_dev, (USERDATA_OFFSET+entry*SECTORSIZE+pageno*PAGESIZE), databuf, PAGESIZE);
for (i=0; i<PAGESIZE; i++)
databuf[i] = bitswap8(databuf[i]);
if (retval != 0)
return retval;
} else {

6
software/sys_controller/ossc/utils.c
View File

@ -25,6 +25,12 @@
#include "sysconfig.h"
#include "io.h"
inline unsigned char bitswap8(unsigned char v)
{
return ((v * 0x0802LU & 0x22110LU) |
(v * 0x8020LU & 0x88440LU)) * 0x10101LU >> 16;
}
alt_u32 bswap32(alt_u32 w)
{
return (((w << 24) & 0xff000000) |

2
software/sys_controller/ossc/utils.h
View File

@ -24,7 +24,7 @@
#define PRINTF_BUFSIZE 512
unsigned char bitswap8(unsigned char v);
inline unsigned char bitswap8(unsigned char v);
alt_u32 bswap32(alt_u32 w);

12
software/sys_controller_bsp/Makefile
View File

@ -225,12 +225,12 @@ altera_avalon_timer_driver_C_LIB_SRCS := \
$(altera_avalon_timer_driver_SRCS_ROOT)/src/altera_avalon_timer_ts.c \
$(altera_avalon_timer_driver_SRCS_ROOT)/src/altera_avalon_timer_vars.c
# altera_epcq_controller_mod_driver sources root
altera_epcq_controller_mod_driver_SRCS_ROOT := drivers
# altera_epcq_controller2_driver sources root
altera_epcq_controller2_driver_SRCS_ROOT := drivers
# altera_epcq_controller_mod_driver sources
altera_epcq_controller_mod_driver_C_LIB_SRCS := \
$(altera_epcq_controller_mod_driver_SRCS_ROOT)/src/altera_epcq_controller_mod.c
# altera_epcq_controller2_driver sources
altera_epcq_controller2_driver_C_LIB_SRCS := \
$(altera_epcq_controller2_driver_SRCS_ROOT)/src/altera_epcq_controller2.c
# altera_nios2_gen2_hal_driver sources root
altera_nios2_gen2_hal_driver_SRCS_ROOT := HAL
@ -276,7 +276,7 @@ nios2_hw_crc32_driver_SRCS_ROOT := drivers
COMPONENT_C_LIB_SRCS += \
$(altera_avalon_jtag_uart_driver_C_LIB_SRCS) \
$(altera_avalon_timer_driver_C_LIB_SRCS) \
$(altera_epcq_controller_mod_driver_C_LIB_SRCS) \
$(altera_epcq_controller2_driver_C_LIB_SRCS) \
$(altera_nios2_gen2_hal_driver_C_LIB_SRCS) \
$(hal_C_LIB_SRCS) \
$(i2c_opencores_driver_C_LIB_SRCS) \

6
software/sys_controller_bsp/alt_sys_init.c
View File

@ -61,7 +61,7 @@
//#include "altera_nios2_gen2_irq.h"
#include "altera_avalon_jtag_uart.h"
#include "altera_avalon_timer.h"
#include "altera_epcq_controller_mod.h"
#include "altera_epcq_controller2.h"
#include "i2c_opencores.h"
/*
@ -71,7 +71,7 @@
//ALTERA_NIOS2_GEN2_IRQ_INSTANCE ( NIOS2_QSYS_0, nios2_qsys_0);
ALTERA_AVALON_JTAG_UART_INSTANCE ( JTAG_UART_0, jtag_uart_0);
ALTERA_AVALON_TIMER_INSTANCE ( TIMER_0, timer_0);
ALTERA_EPCQ_CONTROLLER_MOD_AVL_MEM_AVL_CSR_INSTANCE ( EPCQ_CONTROLLER_0, EPCQ_CONTROLLER_0_AVL_MEM, EPCQ_CONTROLLER_0_AVL_CSR, epcq_controller_0);
ALTERA_EPCQ_CONTROLLER2_AVL_MEM_AVL_CSR_INSTANCE ( EPCQ_CONTROLLER2_0, EPCQ_CONTROLLER2_0_AVL_MEM, EPCQ_CONTROLLER2_0_AVL_CSR, epcq_controller2_0);
I2C_OPENCORES_INSTANCE ( I2C_OPENCORES_0, i2c_opencores_0);
I2C_OPENCORES_INSTANCE ( I2C_OPENCORES_1, i2c_opencores_1);
@ -98,7 +98,7 @@ void alt_sys_init( void )
{
ALTERA_AVALON_TIMER_INIT ( TIMER_0, timer_0);
ALTERA_AVALON_JTAG_UART_INIT ( JTAG_UART_0, jtag_uart_0);
ALTERA_EPCQ_CONTROLLER_MOD_INIT ( EPCQ_CONTROLLER_0, epcq_controller_0);
ALTERA_EPCQ_CONTROLLER2_INIT ( EPCQ_CONTROLLER2_0, epcq_controller2_0);
I2C_OPENCORES_INIT ( I2C_OPENCORES_0, i2c_opencores_0);
I2C_OPENCORES_INIT ( I2C_OPENCORES_1, i2c_opencores_1);
}

44
ip/altera_epcq_controller_mod/HAL/inc/altera_epcq_controller_mod.h → software/sys_controller_bsp/drivers/inc/altera_epcq_controller2.h
View File

@ -28,8 +28,8 @@
* *
******************************************************************************/
#ifndef __ALT_EPCQ_CONTROLLER_H__
#define __ALT_EPCQ_CONTROLLER_H__
#ifndef __ALT_EPCQ_CONTROLLER2_H__
#define __ALT_EPCQ_CONTROLLER2_H__
#include "alt_types.h"
#include "sys/alt_flash_dev.h"
@ -43,7 +43,7 @@ extern "C"
/**
* Description of the EPCQ controller
*/
typedef struct alt_epcq_controller_dev
typedef struct alt_epcq_controller2_dev
{
alt_flash_dev dev;
@ -56,25 +56,25 @@ typedef struct alt_epcq_controller_dev
alt_u32 sector_size; /** size of each flash sector */
alt_u32 page_size; /** page size */
alt_u32 silicon_id; /** ID of silicon used with EPCQ IP */
} alt_epcq_controller_dev;
} alt_epcq_controller2_dev;
/**
* Macros used by alt_sys_init.c to create data storage for driver instance
*/
#define ALTERA_EPCQ_CONTROLLER_MOD_AVL_MEM_AVL_CSR_INSTANCE(epcq_name, avl_mem, avl_csr, epcq_dev) \
alt_epcq_controller_dev epcq_dev = \
#define ALTERA_EPCQ_CONTROLLER2_AVL_MEM_AVL_CSR_INSTANCE(epcq_name, avl_mem, avl_csr, epcq_dev) \
static alt_epcq_controller2_dev epcq_dev = \
{ \
.dev = { \
.llist = ALT_LLIST_ENTRY, \
.name = avl_mem##_NAME, \
.write = alt_epcq_controller_write, \
.read = alt_epcq_controller_read, \
.get_info = alt_epcq_controller_get_info, \
.erase_block = alt_epcq_controller_erase_block, \
.write_block = alt_epcq_controller_write_block, \
.write = alt_epcq_controller2_write, \
.read = alt_epcq_controller2_read, \
.get_info = alt_epcq_controller2_get_info, \
.erase_block = alt_epcq_controller2_erase_block, \
.write_block = alt_epcq_controller2_write_block, \
.base_addr = ((void*)(avl_mem##_BASE)), \
.length = ((int)(avl_mem##_SPAN)), \
.lock = alt_epcq_controller_lock , \
.lock = alt_epcq_controller2_lock , \
}, \
.data_base = ((alt_u32)(avl_mem##_BASE)), \
.data_end = ((alt_u32)(avl_mem##_BASE) + (alt_u32)(avl_mem##_SPAN)), \
@ -94,33 +94,33 @@ alt_epcq_controller_dev epcq_dev =
of the Nios II Software Developer's Handbook.
*/
int alt_epcq_controller_read(alt_flash_dev *flash_info, int offset, void *dest_addr, int length);
int alt_epcq_controller2_read(alt_flash_dev *flash_info, int offset, void *dest_addr, int length);
int alt_epcq_controller_get_info(alt_flash_fd *fd, flash_region **info, int *number_of_regions);
int alt_epcq_controller2_get_info(alt_flash_fd *fd, flash_region **info, int *number_of_regions);
int alt_epcq_controller_erase_block(alt_flash_dev *flash_info, int block_offset);
int alt_epcq_controller2_erase_block(alt_flash_dev *flash_info, int block_offset);
int alt_epcq_controller_write_block(alt_flash_dev *flash_info, int block_offset, int data_offset, const void *data, int length);
int alt_epcq_controller2_write_block(alt_flash_dev *flash_info, int block_offset, int data_offset, const void *data, int length);
int alt_epcq_controller_write(alt_flash_dev *flash_info, int offset, const void *src_addr, int length);
int alt_epcq_controller2_write(alt_flash_dev *flash_info, int offset, const void *src_addr, int length);
int alt_epcq_controller_lock(alt_flash_dev *flash_info, alt_u32 sectors_to_lock);
int alt_epcq_controller2_lock(alt_flash_dev *flash_info, alt_u32 sectors_to_lock);
/*
* Initialization function
*/
extern alt_32 altera_epcq_controller_init(alt_epcq_controller_dev *dev);
extern alt_32 altera_epcq_controller2_init(alt_epcq_controller2_dev *dev);
/*
* alt_sys_init.c will call this macro automatically initialize the driver instance
*/
#define ALTERA_EPCQ_CONTROLLER_MOD_INIT(name, dev) \
altera_epcq_controller_init(&dev);
#define ALTERA_EPCQ_CONTROLLER2_INIT(name, dev) \
altera_epcq_controller2_init(&dev);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALT_EPCQ_CONTROLLER_H__ */
#endif /* __ALT_EPCQ_CONTROLLER2_H__ */

149
ip/altera_epcq_controller_mod/inc/altera_epcq_controller_mod_regs.h → software/sys_controller_bsp/drivers/inc/altera_epcq_controller2_regs.h
View File

@ -28,8 +28,8 @@
* *
******************************************************************************/
#ifndef __ALTERA_EPCQ_CONTROLLER_REGS_H__
#define __ALTERA_EPCQ_CONTROLLER_REGS_H__
#ifndef __ALTERA_EPCQ_CONTROLLER2_REGS_H__
#define __ALTERA_EPCQ_CONTROLLER2_REGS_H__
#include <io.h>
@ -41,31 +41,31 @@
* data sheet,
*
*/
#define ALTERA_EPCQ_CONTROLLER_STATUS_REG (0x0)
#define ALTERA_EPCQ_CONTROLLER2_STATUS_REG (0x0)
/*
* EPCQ_RD_STATUS register access macros
*/
#define IOADDR_ALTERA_EPCQ_CONTROLLER_STATUS(base) \
__IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_STATUS_REG)
#define IOADDR_ALTERA_EPCQ_CONTROLLER2_STATUS(base) \
__IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER2_STATUS_REG)
#define IORD_ALTERA_EPCQ_CONTROLLER_STATUS(base) \
IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_STATUS_REG)
#define IORD_ALTERA_EPCQ_CONTROLLER2_STATUS(base) \
IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_STATUS_REG)
#define IOWR_ALTERA_EPCQ_CONTROLLER_STATUS(base, data) \
IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_STATUS_REG, data)
#define IOWR_ALTERA_EPCQ_CONTROLLER2_STATUS(base, data) \
IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_STATUS_REG, data)
/*
* EPCQ_RD_STATUS register description macros
*/
/** Write in progress bit */
#define ALTERA_EPCQ_CONTROLLER_STATUS_WIP_MASK (0x00000001)
#define ALTERA_EPCQ_CONTROLLER_STATUS_WIP_AVAILABLE (0x00000000)
#define ALTERA_EPCQ_CONTROLLER_STATUS_WIP_BUSY (0x00000001)
#define ALTERA_EPCQ_CONTROLLER2_STATUS_WIP_MASK (0x00000001)
#define ALTERA_EPCQ_CONTROLLER2_STATUS_WIP_AVAILABLE (0x00000000)
#define ALTERA_EPCQ_CONTROLLER2_STATUS_WIP_BUSY (0x00000001)
/** When to time out a poll of the write in progress bit */
/* 0.7 sec time out */
#define ALTERA_EPCQ_CONTROLLER_1US_TIMEOUT_VALUE 700000
#define ALTERA_EPCQ_CONTROLLER2_1US_TIMEOUT_VALUE 700000
/*
* EPCQ_RD_SID register offset
@ -77,19 +77,19 @@
* This register is valid only if the device is an EPCS.
*
*/
#define ALTERA_EPCQ_CONTROLLER_SID_REG (0x4)
#define ALTERA_EPCQ_CONTROLLER2_SID_REG (0x4)
/*
* EPCQ_RD_SID register access macros
*/
#define IOADDR_ALTERA_EPCQ_CONTROLLER_SID(base) \
__IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_SID_REG)
#define IOADDR_ALTERA_EPCQ_CONTROLLER2_SID(base) \
__IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER2_SID_REG)
#define IORD_ALTERA_EPCQ_CONTROLLER_SID(base) \
IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_SID_REG)
#define IORD_ALTERA_EPCQ_CONTROLLER2_SID(base) \
IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_SID_REG)
#define IOWR_ALTERA_EPCQ_CONTROLLER_SID(base, data) \
IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_SID_REG, data)
#define IOWR_ALTERA_EPCQ_CONTROLLER2_SID(base, data) \
IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_SID_REG, data)
/*
* EPCQ_RD_SID register description macros
@ -97,10 +97,10 @@
* Specific device values obtained from Table 14 of:
* "Serial Configuration (EPCS) Devices Datasheet"
*/
#define ALTERA_EPCQ_CONTROLLER_SID_MASK (0x000000FF)
#define ALTERA_EPCQ_CONTROLLER_SID_EPCS16 (0x00000014)
#define ALTERA_EPCQ_CONTROLLER_SID_EPCS64 (0x00000016)
#define ALTERA_EPCQ_CONTROLLER_SID_EPCS128 (0x00000018)
#define ALTERA_EPCQ_CONTROLLER2_SID_MASK (0x000000FF)
#define ALTERA_EPCQ_CONTROLLER2_SID_EPCS16 (0x00000014)
#define ALTERA_EPCQ_CONTROLLER2_SID_EPCS64 (0x00000016)
#define ALTERA_EPCQ_CONTROLLER2_SID_EPCS128 (0x00000018)
/*
* EPCQ_RD_RDID register offset
@ -112,19 +112,19 @@
* This register is only valid if the device is an EPCQ.
*
*/
#define ALTERA_EPCQ_CONTROLLER_RDID_REG (0x8)
#define ALTERA_EPCQ_CONTROLLER2_RDID_REG (0x8)
/*
* EPCQ_RD_RDID register access macros
*/
#define IOADDR_ALTERA_EPCQ_CONTROLLER_RDID(base) \
__IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_RDID_REG)
#define IOADDR_ALTERA_EPCQ_CONTROLLER2_RDID(base) \
__IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER2_RDID_REG)
#define IORD_ALTERA_EPCQ_CONTROLLER_RDID(base) \
IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_RDID_REG)
#define IORD_ALTERA_EPCQ_CONTROLLER2_RDID(base) \
IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_RDID_REG)
#define IOWR_ALTERA_EPCQ_CONTROLLER_RDID(base, data) \
IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_RDID_REG, data)
#define IOWR_ALTERA_EPCQ_CONTROLLER2_RDID(base, data) \
IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_RDID_REG, data)
/*
* EPCQ_RD_RDID register description macros
@ -133,14 +133,14 @@
* "Quad-Serial Configuration (EPCQ (www.altera.com/literature/hb/cfg/cfg_cf52012.pdf))
* Devices Datasheet"
*/
#define ALTERA_EPCQ_CONTROLLER_RDID_MASK (0x000000FF)
#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ16 (0x00000015)
#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ32 (0x00000016)
#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ64 (0x00000017)
#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ128 (0x00000018)
#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ256 (0x00000019)
#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ512 (0x00000020)
#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ1024 (0x00000021)
#define ALTERA_EPCQ_CONTROLLER2_RDID_MASK (0x000000FF)
#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ16 (0x00000015)
#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ32 (0x00000016)
#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ64 (0x00000017)
#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ128 (0x00000018)
#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ256 (0x00000019)
#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ512 (0x00000020)
#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ1024 (0x00000021)
/*
* EPCQ_MEM_OP register offset
@ -148,30 +148,31 @@
* The EPCQ_MEM_OP register is used to do memory protect and erase operations
*
*/
#define ALTERA_EPCQ_CONTROLLER_MEM_OP_REG (0xC)
#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_REG (0xC)
/*
* EPCQ_MEM_OP register access macros
*/
#define IOADDR_ALTERA_EPCQ_CONTROLLER_MEM_OP(base) \
__IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_MEM_OP_REG)
#define IOADDR_ALTERA_EPCQ_CONTROLLER2_MEM_OP(base) \
__IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER2_MEM_OP_REG)
#define IORD_ALTERA_EPCQ_CONTROLLER_MEM_OP(base) \
IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_MEM_OP_REG)
#define IORD_ALTERA_EPCQ_CONTROLLER2_MEM_OP(base) \
IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_MEM_OP_REG)
#define IOWR_ALTERA_EPCQ_CONTROLLER_MEM_OP(base, data) \
IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_MEM_OP_REG, data)
#define IOWR_ALTERA_EPCQ_CONTROLLER2_MEM_OP(base, data) \
IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_MEM_OP_REG, data)
/*
* EPCQ_MEM_OP register description macros
*/
#define ALTERA_EPCQ_CONTROLLER_MEM_OP_CMD_MASK (0x00000003)
#define ALTERA_EPCQ_CONTROLLER_MEM_OP_BULK_ERASE_CMD (0x00000001)
#define ALTERA_EPCQ_CONTROLLER_MEM_OP_SECTOR_ERASE_CMD (0x00000002)
#define ALTERA_EPCQ_CONTROLLER_MEM_OP_SECTOR_PROTECT_CMD (0x00000003)
#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_CMD_MASK (0x00000003)
#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_BULK_ERASE_CMD (0x00000001)
#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_ERASE_CMD (0x00000002)
#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_PROTECT_CMD (0x00000003)
#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_WRITE_ENABLE_CMD (0x00000004)
/** see datasheet for sector values */
#define ALTERA_EPCQ_CONTROLLER_MEM_OP_SECTOR_VALUE_MASK (0x00FFFF00)
#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_VALUE_MASK (0x00FFFF00)
/*
* EPCQ_ISR register offset
@ -180,28 +181,28 @@
* operation triggered an interrupt
*
*/
#define ALTERA_EPCQ_CONTROLLER_ISR_REG (0x10)
#define ALTERA_EPCQ_CONTROLLER2_ISR_REG (0x10)
/*
* EPCQ_ISR register access macros
*/
#define IOADDR_ALTERA_EPCQ_CONTROLLER_ISR(base) \
__IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_ISR_REG)
#define IOADDR_ALTERA_EPCQ_CONTROLLER2_ISR(base) \
__IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER2_ISR_REG)
#define IORD_ALTERA_EPCQ_CONTROLLER_ISR(base) \
IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_ISR_REG)
#define IORD_ALTERA_EPCQ_CONTROLLER2_ISR(base) \
IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_ISR_REG)
#define IOWR_ALTERA_EPCQ_CONTROLLER_ISR(base, data) \
IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_ISR_REG, data)
#define IOWR_ALTERA_EPCQ_CONTROLLER2_ISR(base, data) \
IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_ISR_REG, data)
/*
* EPCQ_ISR register description macros
*/
#define ALTERA_EPCQ_CONTROLLER_ISR_ILLEGAL_ERASE_MASK (0x00000001)
#define ALTERA_EPCQ_CONTROLLER_ISR_ILLEGAL_ERASE_ACTIVE (0x00000001)
#define ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_ERASE_MASK (0x00000001)
#define ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_ERASE_ACTIVE (0x00000001)
#define ALTERA_EPCQ_CONTROLLER_ISR_ILLEGAL_WRITE_MASK (0x00000002)
#define ALTERA_EPCQ_CONTROLLER_ISR_ILLEGAL_WRITE_ACTIVE (0x00000002)
#define ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_WRITE_MASK (0x00000002)
#define ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_WRITE_ACTIVE (0x00000002)
/*
@ -211,28 +212,28 @@
* interrupts.
*
*/
#define ALTERA_EPCQ_CONTROLLER_IMR_REG (0x14)
#define ALTERA_EPCQ_CONTROLLER2_IMR_REG (0x14)
/*
* EPCQ_IMR register access macros
*/
#define IOADDR_ALTERA_EPCQ_CONTROLLER_IMR(base) \
__IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_IMR_REG)
#define IOADDR_ALTERA_EPCQ_CONTROLLER2_IMR(base) \
__IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER2_IMR_REG)
#define IORD_ALTERA_EPCQ_CONTROLLER_IMR(base) \
IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_IMR_REG)
#define IORD_ALTERA_EPCQ_CONTROLLER2_IMR(base) \
IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_IMR_REG)
#define IOWR_ALTERA_EPCQ_CONTROLLER_IMR(base, data) \
IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_IMR_REG, data)
#define IOWR_ALTERA_EPCQ_CONTROLLER2_IMR(base, data) \
IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_IMR_REG, data)
/*
* EPCQ_IMR register description macros
*/
#define ALTERA_EPCQ_CONTROLLER_IMR_ILLEGAL_ERASE_MASK (0x00000001)
#define ALTERA_EPCQ_CONTROLLER_IMR_ILLEGAL_ERASE_ENABLED (0x00000001)
#define ALTERA_EPCQ_CONTROLLER2_IMR_ILLEGAL_ERASE_MASK (0x00000001)
#define ALTERA_EPCQ_CONTROLLER2_IMR_ILLEGAL_ERASE_ENABLED (0x00000001)
#define ALTERA_EPCQ_CONTROLLER_IMR_ILLEGAL_WRITE_MASK (0x00000002)
#define ALTERA_EPCQ_CONTROLLER_IMR_ILLEGAL_WRITE_ENABLED (0x00000002)
#define ALTERA_EPCQ_CONTROLLER2_IMR_ILLEGAL_WRITE_MASK (0x00000002)
#define ALTERA_EPCQ_CONTROLLER2_IMR_ILLEGAL_WRITE_ENABLED (0x00000002)
/*
* EPCQ_CHIP_SELECT register offset
@ -257,4 +258,4 @@
#define ALTERA_EPCQ_CHIP2_SELECT (0x00000002)
#define ALTERA_EPCQ_CHIP3_SELECT (0x00000003)
#endif /* __ALTERA_EPCQ_CONTROLLER_REGS_H__ */
#endif /* __ALTERA_EPCQ_CONTROLLER2_REGS_H__ */

1
software/sys_controller_bsp/drivers/inc/altera_epcq_controller_mod.h
View File

@ -1 +0,0 @@
../../../../ip/altera_epcq_controller_mod/HAL/inc/altera_epcq_controller_mod.h

1
software/sys_controller_bsp/drivers/inc/altera_epcq_controller_mod_regs.h
View File

@ -1 +0,0 @@
../../../../ip/altera_epcq_controller_mod/inc/altera_epcq_controller_mod_regs.h

596
ip/altera_epcq_controller_mod/HAL/src/altera_epcq_controller_mod.c → software/sys_controller_bsp/drivers/src/altera_epcq_controller2.c
View File

@ -34,16 +34,15 @@
#include <stddef.h>
#include "sys/param.h"
#include "alt_types.h"
#include "altera_epcq_controller_mod_regs.h"
#include "altera_epcq_controller_mod.h"
#include "altera_epcq_controller2_regs.h"
#include "altera_epcq_controller2.h"
#include "priv/alt_busy_sleep.h"
#include "sys/alt_debug.h"
#include "sys/alt_cache.h"
ALT_INLINE alt_32 static alt_epcq_validate_read_write_arguments(alt_epcq_controller_dev *flash_info,alt_u32 offset, alt_u32 length);
alt_32 static alt_epcq_poll_for_write_in_progress(alt_epcq_controller_dev* epcq_flash_info);
ALT_INLINE unsigned char static bitswap8(unsigned char v);
ALT_INLINE alt_32 static alt_epcq_validate_read_write_arguments(alt_epcq_controller2_dev *flash_info,alt_u32 offset, alt_u32 length);
alt_32 static alt_epcq_poll_for_write_in_progress(alt_epcq_controller2_dev* epcq_flash_info);
/*
* Public API
@ -55,7 +54,7 @@ ALT_INLINE unsigned char static bitswap8(unsigned char v);
/**
* alt_epcq_controller_lock
* alt_epcq_controller2_lock
*
* Locks the range of the memory sectors, which
* protected from write and erase.
@ -72,52 +71,52 @@ ALT_INLINE unsigned char static bitswap8(unsigned char v);
* -ETIME -> Time out and skipping the looping after 0.7 sec.
* -ENOLCK -> Sectors lock failed.
**/
int alt_epcq_controller_lock(alt_flash_dev *flash_info, alt_u32 sectors_to_lock)
int alt_epcq_controller2_lock(alt_flash_dev *flash_info, alt_u32 sectors_to_lock)
{
alt_u32 mem_op_value = 0; /* value to write to EPCQ_MEM_OP register */
alt_epcq_controller_dev* epcq_flash_info = NULL;
alt_epcq_controller2_dev* epcq_flash_info = NULL;
alt_u32 result = 0;
alt_32 status = 0;
/* return -EINVAL if flash_info is NULL */
if(NULL == flash_info || 0 > sectors_to_lock)
{
return -EINVAL;
return -EINVAL;
}
epcq_flash_info = (alt_epcq_controller_dev*)flash_info;
epcq_flash_info = (alt_epcq_controller2_dev*)flash_info;
/* sector value should occupy bits 17:8 */
mem_op_value = sectors_to_lock << 8;
/* sector protect commands 0b11 occupies lower 2 bits */
mem_op_value |= ALTERA_EPCQ_CONTROLLER_MEM_OP_SECTOR_PROTECT_CMD;
mem_op_value |= ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_PROTECT_CMD;
/* write sector protect command to EPCQ_MEM_OP register to protect sectors */
IOWR_ALTERA_EPCQ_CONTROLLER_MEM_OP(epcq_flash_info->csr_base, mem_op_value);
IOWR_ALTERA_EPCQ_CONTROLLER2_MEM_OP(epcq_flash_info->csr_base, mem_op_value);
/* poll write in progress to make sure no operation is in progress */
status = alt_epcq_poll_for_write_in_progress(epcq_flash_info);
if(status != 0)
{
return status;
return status;
}
status = IORD_ALTERA_EPCQ_CONTROLLER_STATUS(epcq_flash_info->csr_base);
result |= (status >> 2) & 0x07; /* extract out BP3 - BP0 */
result |= (status >> 3) & 0x08; /* extract out BP4 */
status = IORD_ALTERA_EPCQ_CONTROLLER2_STATUS(epcq_flash_info->csr_base);
result |= (status >> 2) & 0x07; /* extract out BP3 - BP0 */
result |= (status >> 3) & 0x08; /* extract out BP4 */
result |= (status >> 1) & 0x10; /* extract out TOP/BOTTOM bit */
if(result != sectors_to_lock)
{
return -ENOLCK;
}
if(result != sectors_to_lock)
{
/*return -ENOLCK;*/
}
return 0;
}
/**
* alt_epcq_controller_get_info
* alt_epcq_controller2_get_info
*
* Pass the table of erase blocks to the user. This flash will return a single
* flash_region that gives the number and size of sectors for the device used.
@ -134,19 +133,19 @@ int alt_epcq_controller_lock(alt_flash_dev *flash_info, alt_u32 sectors_to_lock)
* -EINVAL -> Invalid arguments
* -EIO -> Could be hardware problem.
**/
int alt_epcq_controller_get_info
int alt_epcq_controller2_get_info
(
alt_flash_fd *fd, /** flash device descriptor */
flash_region **info, /** pointer to flash_region will be stored here */
int *number_of_regions /** number of regions will be stored here */
)
{
alt_flash_dev* flash = NULL;
/* return -EINVAL if fd,info and number_of_regions are NULL */
if(NULL == fd || NULL == info || NULL == number_of_regions)
alt_flash_dev* flash = NULL;
/* return -EINVAL if fd,info and number_of_regions are NULL */
if(NULL == fd || NULL == info || NULL == number_of_regions)
{
return -EINVAL;
return -EINVAL;
}
flash = (alt_flash_dev*)fd;
@ -166,7 +165,7 @@ int alt_epcq_controller_get_info
}
/**
* alt_epcq_controller_erase_block
* alt_epcq_controller2_erase_block
*
* This function erases a single flash sector.
*
@ -179,20 +178,20 @@ int alt_epcq_controller_get_info
* -EINVAL -> Invalid arguments
* -EIO -> write failed, sector might be protected
**/
int alt_epcq_controller_erase_block(alt_flash_dev *flash_info, int block_offset)
int alt_epcq_controller2_erase_block(alt_flash_dev *flash_info, int block_offset)
{
alt_32 ret_code = 0;
alt_u32 mem_op_value = 0; /* value to write to EPCQ_MEM_OP register */
alt_epcq_controller_dev* epcq_flash_info = NULL;
alt_epcq_controller2_dev* epcq_flash_info = NULL;
alt_u32 sector_number = 0;
/* return -EINVAL if flash_info is NULL */
if(NULL == flash_info)
{
return -EINVAL;
return -EINVAL;
}
epcq_flash_info = (alt_epcq_controller_dev*)flash_info;
epcq_flash_info = (alt_epcq_controller2_dev*)flash_info;
/*
* Sanity checks that block_offset is within the flash memory span and that the
@ -203,38 +202,47 @@ int alt_epcq_controller_erase_block(alt_flash_dev *flash_info, int block_offset)
|| (block_offset >= epcq_flash_info->size_in_bytes)
|| (block_offset & (epcq_flash_info->sector_size - 1)) != 0)
{
return -EINVAL;
return -EINVAL;
}
/* calculate current sector/block number */
sector_number = (block_offset/(epcq_flash_info->sector_size));
/* sector value should occupy bits 23:8 */
mem_op_value = (sector_number << 8) & ALTERA_EPCQ_CONTROLLER_MEM_OP_SECTOR_VALUE_MASK;
/* sector erase commands 0b10 occupies lower 2 bits */
mem_op_value |= ALTERA_EPCQ_CONTROLLER_MEM_OP_SECTOR_ERASE_CMD;
mem_op_value = (sector_number << 8) & ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_VALUE_MASK;
/* write enable command */
mem_op_value |= ALTERA_EPCQ_CONTROLLER2_MEM_OP_WRITE_ENABLE_CMD;
/* write sector erase command to EPCQ_MEM_OP register to erase sector "sector_number" */
IOWR_ALTERA_EPCQ_CONTROLLER_MEM_OP(epcq_flash_info->csr_base, mem_op_value);
IOWR_ALTERA_EPCQ_CONTROLLER2_MEM_OP(epcq_flash_info->csr_base, mem_op_value);
/* sector value should occupy bits 23:8 */
mem_op_value = (sector_number << 8) & ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_VALUE_MASK;
/* sector erase commands 0b10 occupies lower 2 bits */
mem_op_value |= ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_ERASE_CMD;
/* write sector erase command to EPCQ_MEM_OP register to erase sector "sector_number" */
IOWR_ALTERA_EPCQ_CONTROLLER2_MEM_OP(epcq_flash_info->csr_base, mem_op_value);
/* check whether erase triggered a illegal erase interrupt */
if((IORD_ALTERA_EPCQ_CONTROLLER_ISR(epcq_flash_info->csr_base) &
ALTERA_EPCQ_CONTROLLER_ISR_ILLEGAL_ERASE_MASK) ==
ALTERA_EPCQ_CONTROLLER_ISR_ILLEGAL_ERASE_ACTIVE)
if((IORD_ALTERA_EPCQ_CONTROLLER2_ISR(epcq_flash_info->csr_base) &
ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_ERASE_MASK) ==
ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_ERASE_ACTIVE)
{
/* clear register */
/* EPCQ_ISR access is write one to clear (W1C) */
IOWR_ALTERA_EPCQ_CONTROLLER_ISR(epcq_flash_info->csr_base,
ALTERA_EPCQ_CONTROLLER_ISR_ILLEGAL_ERASE_MASK );
return -EIO; /* erase failed, sector might be protected */
/* clear register */
/* EPCQ_ISR access is write one to clear (W1C) */
IOWR_ALTERA_EPCQ_CONTROLLER2_ISR(epcq_flash_info->csr_base,
ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_ERASE_MASK );
return -EIO; /* erase failed, sector might be protected */
}
return ret_code;
}
/**
* alt_epcq_controller_write_block
* alt_epcq_controller2_write_block
*
* This function writes one block/sector of data to flash. The length of the write can NOT
* spill into the adjacent sector.
@ -254,7 +262,7 @@ int alt_epcq_controller_erase_block(alt_flash_dev *flash_info, int block_offset)
* -EINVAL -> Invalid arguments
* -EIO -> write failed, sector might be protected
**/
int alt_epcq_controller_write_block
int alt_epcq_controller2_write_block
(
alt_flash_dev *flash_info, /** flash device info */
int block_offset, /** sector/block offset in byte addressing */
@ -267,8 +275,8 @@ int alt_epcq_controller_write_block
alt_u32 remaining_length = length; /** length left to write */
alt_u32 write_offset = data_offset; /** offset into flash to write too */
alt_epcq_controller_dev *epcq_flash_info = (alt_epcq_controller_dev*)flash_info;
alt_epcq_controller2_dev *epcq_flash_info = (alt_epcq_controller2_dev*)flash_info;
/*
* Sanity checks that data offset is not larger then a sector, that block offset is
* sector aligned and within the valid flash memory range and a write doesn't spill into
@ -284,7 +292,7 @@ int alt_epcq_controller_write_block
|| length < 0
|| (block_offset & (epcq_flash_info->sector_size - 1)) != 0)
{
return -EINVAL;
return -EINVAL;
}
/*
@ -294,20 +302,20 @@ int alt_epcq_controller_write_block
*/
while (remaining_length > 0)
{
alt_u32 word_to_write = 0xFFFFFFFF; /** initialize word to write to blank word */
alt_u32 padding = 0; /** bytes to pad the next word that is written */
alt_u32 bytes_to_copy = sizeof(alt_u32); /** number of bytes from source to copy */
alt_u32 word_to_write = 0xFFFFFFFF; /** initialize word to write to blank word */
alt_u32 padding = 0; /** bytes to pad the next word that is written */
alt_u32 bytes_to_copy = sizeof(alt_u32); /** number of bytes from source to copy */
/*
* we need to make sure the write is word aligned
* this should only be true at most 1 time
*/
* this should only be true at most 1 time
*/
if (0 != (write_offset & (sizeof(alt_u32) - 1)))
{
/*
* data is not word aligned
* calculate padding bytes need to add before start of a data offset
*/
/*
* data is not word aligned
* calculate padding bytes need to add before start of a data offset
*/
padding = write_offset & (sizeof(alt_u32) - 1);
/* update variables to account for padding being added */
@ -315,46 +323,46 @@ int alt_epcq_controller_write_block
if(bytes_to_copy > remaining_length)
{
bytes_to_copy = remaining_length;
bytes_to_copy = remaining_length;
}
write_offset = write_offset - padding;
if(0 != (write_offset & (sizeof(alt_u32) - 1)))
{
return -EINVAL;
return -EINVAL;
}
}
else
{
if(bytes_to_copy > remaining_length)
{
bytes_to_copy = remaining_length;
bytes_to_copy = remaining_length;
}
}
/* prepare the word to be written */
memcpy((((void*)&word_to_write)) + padding, ((void*)data) + buffer_offset, bytes_to_copy);
// Bit-reverse bytes for flash
for (int i=0; i<bytes_to_copy; i++)
*((unsigned char*)&word_to_write+i) = bitswap8(*((unsigned char*)&word_to_write+i));
/* update offset and length variables */
buffer_offset += bytes_to_copy;
remaining_length -= bytes_to_copy;
/* write to flash 32 bits at a time */
IOWR_32DIRECT(epcq_flash_info->data_base, write_offset, word_to_write);
/* check whether write triggered a illegal write interrupt */
if((IORD_ALTERA_EPCQ_CONTROLLER_ISR(epcq_flash_info->csr_base) &
ALTERA_EPCQ_CONTROLLER_ISR_ILLEGAL_WRITE_MASK) ==
ALTERA_EPCQ_CONTROLLER_ISR_ILLEGAL_WRITE_ACTIVE)
if (IORD_32DIRECT(epcq_flash_info->data_base, write_offset) != word_to_write)
{
/* clear register */
IOWR_ALTERA_EPCQ_CONTROLLER_ISR(epcq_flash_info->csr_base,
ALTERA_EPCQ_CONTROLLER_ISR_ILLEGAL_WRITE_MASK );
return -EIO; /** write failed, sector might be protected */
IOWR_32DIRECT(epcq_flash_info->data_base, write_offset, word_to_write);
}
/* check whether write triggered a illegal write interrupt */
if((IORD_ALTERA_EPCQ_CONTROLLER2_ISR(epcq_flash_info->csr_base) &
ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_WRITE_MASK) ==
ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_WRITE_ACTIVE)
{
/* clear register */
IOWR_ALTERA_EPCQ_CONTROLLER2_ISR(epcq_flash_info->csr_base,
ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_WRITE_MASK );
return -EIO; /** write failed, sector might be protected */
}
/* update current offset */
@ -365,12 +373,12 @@ int alt_epcq_controller_write_block
}
/**
* alt_epcq_controller_write
* alt_epcq_controller2_write
*
* Program the data into the flash at the selected address.
*
* The different between this function and alt_epcq_controller_write_block function
* is that this function (alt_epcq_controller_write) will automatically erase a block as needed
* The different between this function and alt_epcq_controller2_write_block function
* is that this function (alt_epcq_controller2_write) will automatically erase a block as needed
* Arguments:
* - *flash_info: Pointer to EPCQ flash device structure.
* - offset: Byte offset (unaligned access) of write to flash memory. For best performance,
@ -384,7 +392,7 @@ int alt_epcq_controller_write_block
* -EIO -> write failed, sector might be protected
*
**/
int alt_epcq_controller_write(
int alt_epcq_controller2_write(
alt_flash_dev *flash_info, /** device info */
int offset, /** offset of write from base address */
const void *src_addr, /** source buffer */
@ -393,7 +401,7 @@ int alt_epcq_controller_write(
{
alt_32 ret_code = 0;
alt_epcq_controller_dev *epcq_flash_info = NULL;
alt_epcq_controller2_dev *epcq_flash_info = NULL;
alt_u32 write_offset = offset; /** address of next byte to write */
alt_u32 remaining_length = length; /** length of write data left to be written */
@ -401,20 +409,20 @@ int alt_epcq_controller_write(
alt_u32 i = 0;
/* return -EINVAL if flash_info and src_addr are NULL */
if(NULL == flash_info || NULL == src_addr)
if(NULL == flash_info || NULL == src_addr)
{
return -EINVAL;
return -EINVAL;
}
epcq_flash_info = (alt_epcq_controller_dev*)flash_info;
epcq_flash_info = (alt_epcq_controller2_dev*)flash_info;
/* make sure the write parameters are within the bounds of the flash */
ret_code = alt_epcq_validate_read_write_arguments(epcq_flash_info, offset, length);
if(0 != ret_code)
{
return ret_code;
}
if(0 != ret_code)
{
return ret_code;
}
/*
* This loop erases and writes data one sector at a time. We check for write completion
@ -423,13 +431,13 @@ int alt_epcq_controller_write(
for(i = offset/epcq_flash_info->sector_size ; i < epcq_flash_info->number_of_sectors; i++)
{
alt_u32 block_offset = 0; /** block offset in byte addressing */
alt_u32 offset_within_current_sector = 0; /** offset into current sector to write */
alt_u32 offset_within_current_sector = 0; /** offset into current sector to write */
alt_u32 length_to_write = 0; /** length to write to current sector */
if(0 >= remaining_length)
{
break; /* out of data to write */
}
if(0 >= remaining_length)
{
break; /* out of data to write */
}
/* calculate current sector/block offset in byte addressing */
block_offset = write_offset & ~(epcq_flash_info->sector_size - 1);
@ -441,7 +449,7 @@ int alt_epcq_controller_write(
}
/* erase sector */
ret_code = alt_epcq_controller_erase_block(flash_info, block_offset);
ret_code = alt_epcq_controller2_erase_block(flash_info, block_offset);
if(0 != ret_code)
{
@ -453,7 +461,7 @@ int alt_epcq_controller_write(
remaining_length);
/* write data to erased block */
ret_code = alt_epcq_controller_write_block(flash_info, block_offset, write_offset,
ret_code = alt_epcq_controller2_write_block(flash_info, block_offset, write_offset,
src_addr + buffer_offset, length_to_write);
@ -472,7 +480,7 @@ int alt_epcq_controller_write(
}
/**
* alt_epcq_controller_read
* alt_epcq_controller2_read
*
* There's no real need to use this function as opposed to using memcpy directly. It does
* do some sanity checks on the bounds of the read.
@ -487,7 +495,7 @@ int alt_epcq_controller_write(
* 0 -> success
* -EINVAL -> Invalid arguments
**/
int alt_epcq_controller_read
int alt_epcq_controller2_read
(
alt_flash_dev *flash_info, /** device info */
int offset, /** offset of read from base address */
@ -496,34 +504,30 @@ int alt_epcq_controller_read
)
{
alt_32 ret_code = 0;
alt_epcq_controller_dev *epcq_flash_info = NULL;
/* return -EINVAL if flash_info and dest_addr are NULL */
if(NULL == flash_info || NULL == dest_addr)
alt_epcq_controller2_dev *epcq_flash_info = NULL;
/* return -EINVAL if flash_info and dest_addr are NULL */
if(NULL == flash_info || NULL == dest_addr)
{
return -EINVAL;
return -EINVAL;
}
epcq_flash_info = (alt_epcq_controller_dev*)flash_info;
epcq_flash_info = (alt_epcq_controller2_dev*)flash_info;
/* validate arguments */
ret_code = alt_epcq_validate_read_write_arguments(epcq_flash_info, offset, length);
/* validate arguments */
ret_code = alt_epcq_validate_read_write_arguments(epcq_flash_info, offset, length);
/* copy data from flash to destination address */
if(0 == ret_code)
{
memcpy(dest_addr, (alt_u8*)epcq_flash_info->data_base + offset, length);
// Bit-reverse bytes read from flash
for (int i=0; i<length; i++)
*((unsigned char*)dest_addr+i) = bitswap8(*((unsigned char*)dest_addr+i));
}
/* copy data from flash to destination address */
if(0 == ret_code)
{
memcpy(dest_addr, (alt_u8*)epcq_flash_info->data_base + offset, length);
}
return ret_code;
}
/**
* altera_epcq_controller_init
* altera_epcq_controller2_init
*
* alt_sys_init.c will call this function automatically through macro
*
@ -539,147 +543,147 @@ int alt_epcq_controller_read
* -EINVAL -> Invalid arguments.
* -ENODEV -> System is configured incorrectly.
**/
alt_32 altera_epcq_controller_init(alt_epcq_controller_dev *flash)
alt_32 altera_epcq_controller2_init(alt_epcq_controller2_dev *flash)
{
alt_u32 silicon_id = 0;
alt_u32 size_in_bytes = 0;
alt_u32 number_of_sectors = 0;
alt_u32 silicon_id = 0;
alt_u32 size_in_bytes = 0;
alt_u32 number_of_sectors = 0;
/* return -EINVAL if flash is NULL */
if(NULL == flash)
if(NULL == flash)
{
return -EINVAL;
return -EINVAL;
}
/* return -ENODEV if CSR slave is not attached */
if(NULL == (void *)flash->csr_base)
{
return -ENODEV;
}
/* return -ENODEV if CSR slave is not attached */
if(NULL == (void *)flash->csr_base)
{
return -ENODEV;
}
/*
* If flash is an EPCQ device, we read the EPCQ_RD_RDID register for the ID
* If flash is an EPCS device, we read the EPCQ_RD_SID register for the ID
*
* Whether or not the flash is a EPCQ or EPCS is indicated in the system.h. The system.h gets
* this value from the hw.tcl of the IP. If this value is set incorrectly, then things will go
* badly.
*
* In both cases, we can determine the number of sectors, which we can use
* to calculate a size. We compare that size to the system.h value to make sure
* the EPCQ soft IP was configured correctly.
*/
if(0 == flash->is_epcs)
{
/* If we're an EPCQ, we read EPCQ_RD_RDID for the silicon ID */
silicon_id = IORD_ALTERA_EPCQ_CONTROLLER_RDID(flash->csr_base);
silicon_id &= ALTERA_EPCQ_CONTROLLER_RDID_MASK;
/*
* If flash is an EPCQ device, we read the EPCQ_RD_RDID register for the ID
* If flash is an EPCS device, we read the EPCQ_RD_SID register for the ID
*
* Whether or not the flash is a EPCQ or EPCS is indicated in the system.h. The system.h gets
* this value from the hw.tcl of the IP. If this value is set incorrectly, then things will go
* badly.
*
* In both cases, we can determine the number of sectors, which we can use
* to calculate a size. We compare that size to the system.h value to make sure
* the EPCQ soft IP was configured correctly.
*/
if(0 == flash->is_epcs)
{
/* If we're an EPCQ, we read EPCQ_RD_RDID for the silicon ID */
silicon_id = IORD_ALTERA_EPCQ_CONTROLLER2_RDID(flash->csr_base);
silicon_id &= ALTERA_EPCQ_CONTROLLER2_RDID_MASK;
/* Determine which EPCQ device so we can figure out the number of sectors */
/* EPCQ share the same ID for the same capacity*/
switch(silicon_id)
{
case ALTERA_EPCQ_CONTROLLER_RDID_EPCQ16:
{
number_of_sectors = 32;
break;
}
case ALTERA_EPCQ_CONTROLLER_RDID_EPCQ32:
{
number_of_sectors = 64;
break;
}
case ALTERA_EPCQ_CONTROLLER_RDID_EPCQ64:
{
number_of_sectors = 128;
break;
}
case ALTERA_EPCQ_CONTROLLER_RDID_EPCQ128:
{
number_of_sectors = 256;
break;
}
case ALTERA_EPCQ_CONTROLLER_RDID_EPCQ256:
{
number_of_sectors = 512;
break;
}
case ALTERA_EPCQ_CONTROLLER_RDID_EPCQ512:
{
number_of_sectors = 1024;
break;
}
case ALTERA_EPCQ_CONTROLLER_RDID_EPCQ1024:
{
number_of_sectors = 2048;
break;
}
default:
{
return -ENODEV;
}
}
}
else {
/* If we're an EPCS, we read EPCQ_RD_SID for the silicon ID */
silicon_id = IORD_ALTERA_EPCQ_CONTROLLER_SID(flash->csr_base);
silicon_id &= ALTERA_EPCQ_CONTROLLER_SID_MASK;
/* Determine which EPCQ device so we can figure out the number of sectors */
/* EPCQ share the same ID for the same capacity*/
switch(silicon_id)
{
case ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ16:
{
number_of_sectors = 32;
break;
}
case ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ32:
{
number_of_sectors = 64;
break;
}
case ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ64:
{
number_of_sectors = 128;
break;
}
case ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ128:
{
number_of_sectors = 256;
break;
}
case ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ256:
{
number_of_sectors = 512;
break;
}
case ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ512:
{
number_of_sectors = 1024;
break;
}
case ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ1024:
{
number_of_sectors = 2048;
break;
}
default:
{
return -ENODEV;
}
}
}
else {
/* If we're an EPCS, we read EPCQ_RD_SID for the silicon ID */
silicon_id = IORD_ALTERA_EPCQ_CONTROLLER2_SID(flash->csr_base);
silicon_id &= ALTERA_EPCQ_CONTROLLER2_SID_MASK;
/* Determine which EPCS device so we can figure out various properties */
switch(silicon_id)
{
case ALTERA_EPCQ_CONTROLLER_SID_EPCS16:
{
number_of_sectors = 32;
break;
}
case ALTERA_EPCQ_CONTROLLER_SID_EPCS64:
{
number_of_sectors = 128;
break;
}
case ALTERA_EPCQ_CONTROLLER_SID_EPCS128:
{
number_of_sectors = 256;
break;
}
default:
{
return -ENODEV;
}
}
}
/* Determine which EPCS device so we can figure out various properties */
switch(silicon_id)
{
case ALTERA_EPCQ_CONTROLLER2_SID_EPCS16:
{
number_of_sectors = 32;
break;
}
case ALTERA_EPCQ_CONTROLLER2_SID_EPCS64:
{
number_of_sectors = 128;
break;
}
case ALTERA_EPCQ_CONTROLLER2_SID_EPCS128:
{
number_of_sectors = 256;
break;
}
default:
{
return -ENODEV;
}
}
}
/* Calculate size of flash based on number of sectors */
size_in_bytes = number_of_sectors * flash->sector_size;
/* Calculate size of flash based on number of sectors */
size_in_bytes = number_of_sectors * flash->sector_size;
/*
* Make sure calculated size is the same size given in system.h
* Also check number of sectors is the same number given in system.h
* Otherwise the EPCQ IP was not configured correctly
*/
if( size_in_bytes != flash->size_in_bytes ||
number_of_sectors != flash->number_of_sectors)
{
flash->dev.number_of_regions = 0;
return -ENODEV;
}
else
{
flash->silicon_id = silicon_id;
flash->number_of_sectors = number_of_sectors;
/*
* Make sure calculated size is the same size given in system.h
* Also check number of sectors is the same number given in system.h
* Otherwise the EPCQ IP was not configured correctly
*/
if( size_in_bytes != flash->size_in_bytes ||
number_of_sectors != flash->number_of_sectors)
{
flash->dev.number_of_regions = 0;
return -ENODEV;
}
else
{
flash->silicon_id = silicon_id;
flash->number_of_sectors = number_of_sectors;
/*
* populate fields of region_info required to conform to HAL API
* create 1 region that composed of "number_of_sectors" blocks
*/
flash->dev.number_of_regions = 1;
flash->dev.region_info[0].offset = 0;
flash->dev.region_info[0].region_size = size_in_bytes;
flash->dev.region_info[0].number_of_blocks = number_of_sectors;
flash->dev.region_info[0].block_size = flash->sector_size;
}
/*
* populate fields of region_info required to conform to HAL API
* create 1 region that composed of "number_of_sectors" blocks
*/
flash->dev.number_of_regions = 1;
flash->dev.region_info[0].offset = 0;
flash->dev.region_info[0].region_size = size_in_bytes;
flash->dev.region_info[0].number_of_blocks = number_of_sectors;
flash->dev.region_info[0].block_size = flash->sector_size;
}
/*
@ -687,7 +691,7 @@ alt_32 altera_epcq_controller_init(alt_epcq_controller_dev *flash)
*
* Only register the device if it's configured correctly.
*/
alt_flash_device_register(&(flash->dev));
alt_flash_device_register(&(flash->dev));
return 0;
@ -695,9 +699,9 @@ alt_32 altera_epcq_controller_init(alt_epcq_controller_dev *flash)
/*
* Private API
* Private API
*
* Helper functions used by Public API functions.
* Helper functions used by Public API functions.
*
* Arguments:
* - *flash_info: Pointer to EPCQ flash device structure.
@ -713,35 +717,35 @@ alt_32 altera_epcq_controller_init(alt_epcq_controller_dev *flash)
*/
ALT_INLINE alt_32 static alt_epcq_validate_read_write_arguments
(
alt_epcq_controller_dev *flash_info, /** device info */
alt_u32 offset, /** offset of read/write */
alt_u32 length /** length of read/write */
alt_epcq_controller2_dev *flash_info, /** device info */
alt_u32 offset, /** offset of read/write */
alt_u32 length /** length of read/write */
)
{
alt_epcq_controller_dev *epcq_flash_info = NULL;
alt_epcq_controller2_dev *epcq_flash_info = NULL;
alt_u32 start_address = 0;
alt_32 end_address = 0;
/* return -EINVAL if flash_info is NULL */
if(NULL == flash_info)
{
return -EINVAL;
return -EINVAL;
}
epcq_flash_info = (alt_epcq_controller_dev*)flash_info;
epcq_flash_info = (alt_epcq_controller2_dev*)flash_info;
start_address = epcq_flash_info->data_base + offset; /** first address of read or write */
end_address = start_address + length; /** last address of read or write (not inclusive) */
/* make sure start and end address is less then the end address of the flash */
if(
start_address >= epcq_flash_info->data_end ||
end_address > epcq_flash_info->data_end ||
offset < 0 ||
length < 0
start_address >= epcq_flash_info->data_end ||
end_address > epcq_flash_info->data_end ||
offset < 0 ||
length < 0
)
{
return -EINVAL;
return -EINVAL;
}
return 0;
@ -751,14 +755,14 @@ ALT_INLINE alt_32 static alt_epcq_validate_read_write_arguments
* Private function that polls write in progress bit EPCQ_RD_STATUS.
*
* Write in progress will be set if any of the following operations are in progress:
* -WRITE STATUS REGISTER
* -WRITE NONVOLATILE CONFIGURATION REGISTER
* -PROGRAM
* -ERASE
* -WRITE STATUS REGISTER
* -WRITE NONVOLATILE CONFIGURATION REGISTER
* -PROGRAM
* -ERASE
*
* Assumes EPCQ was configured correctly.
*
* If ALTERA_EPCQ_CONTROLLER_1US_TIMEOUT_VALUE is set, the function will time out after
* If ALTERA_EPCQ_CONTROLLER2_1US_TIMEOUT_VALUE is set, the function will time out after
* a period of time determined by that value.
*
* Arguments:
@ -769,44 +773,38 @@ ALT_INLINE alt_32 static alt_epcq_validate_read_write_arguments
* -EINVAL -> Invalid arguments
* -ETIME -> Time out and skipping the looping after 0.7 sec.
*/
alt_32 static alt_epcq_poll_for_write_in_progress(alt_epcq_controller_dev* epcq_flash_info)
alt_32 static alt_epcq_poll_for_write_in_progress(alt_epcq_controller2_dev* epcq_flash_info)
{
/* we'll want to implement timeout if a timeout value is specified */
#if ALTERA_EPCQ_CONTROLLER_1US_TIMEOUT_VALUE > 0
alt_u32 timeout = ALTERA_EPCQ_CONTROLLER_1US_TIMEOUT_VALUE;
alt_u16 counter = 0;
#if ALTERA_EPCQ_CONTROLLER2_1US_TIMEOUT_VALUE > 0
alt_u32 timeout = ALTERA_EPCQ_CONTROLLER2_1US_TIMEOUT_VALUE;
alt_u16 counter = 0;
#endif
/* return -EINVAL if epcq_flash_info is NULL */
if(NULL == epcq_flash_info)
if(NULL == epcq_flash_info)
{
return -EINVAL;
return -EINVAL;
}
/* while Write in Progress bit is set, we wait */
while((IORD_ALTERA_EPCQ_CONTROLLER_STATUS(epcq_flash_info->csr_base) &
ALTERA_EPCQ_CONTROLLER_STATUS_WIP_MASK) ==
ALTERA_EPCQ_CONTROLLER_STATUS_WIP_BUSY)
{
/* while Write in Progress bit is set, we wait */
while((IORD_ALTERA_EPCQ_CONTROLLER2_STATUS(epcq_flash_info->csr_base) &
ALTERA_EPCQ_CONTROLLER2_STATUS_WIP_MASK) ==
ALTERA_EPCQ_CONTROLLER2_STATUS_WIP_BUSY)
{
alt_busy_sleep(1); /* delay 1us */
#if ALTERA_EPCQ_CONTROLLER_1US_TIMEOUT_VALUE > 0
if(timeout <= counter )
{
return -ETIME;
}
counter++;
#if ALTERA_EPCQ_CONTROLLER2_1US_TIMEOUT_VALUE > 0
if(timeout <= counter )
{
return -ETIME;
}
counter++;
#endif
}
}
return 0;
}
ALT_INLINE unsigned char static bitswap8(unsigned char v)
{
return ((v * 0x0802LU & 0x22110LU) |
(v * 0x8020LU & 0x88440LU)) * 0x10101LU >> 16;
return 0;
}

1
software/sys_controller_bsp/drivers/src/altera_epcq_controller_mod.c
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@ -1 +0,0 @@
../../../../ip/altera_epcq_controller_mod/HAL/src/altera_epcq_controller_mod.c

BIN
software/sys_controller_bsp/libhal_bsp.a
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Binary file not shown.

58
software/sys_controller_bsp/system.h
View File

@ -151,7 +151,7 @@
#define __ALTERA_AVALON_ONCHIP_MEMORY2
#define __ALTERA_AVALON_PIO
#define __ALTERA_AVALON_TIMER
#define __ALTERA_EPCQ_CONTROLLER_MOD
#define __ALTERA_EPCQ_CONTROLLER2
#define __ALTERA_NIOS2_GEN2
#define __ALTERA_NIOS_CUSTOM_INSTR_BITSWAP
#define __ALTERA_NIOS_CUSTOM_INSTR_ENDIANCONVERTER
@ -196,43 +196,43 @@
/*
* epcq_controller_0_avl_csr configuration
* epcq_controller2_0_avl_csr configuration
*
*/
#define ALT_MODULE_CLASS_epcq_controller_0_avl_csr altera_epcq_controller_mod
#define EPCQ_CONTROLLER_0_AVL_CSR_BASE 0x20100
#define EPCQ_CONTROLLER_0_AVL_CSR_FLASH_TYPE "EPCS16"
#define EPCQ_CONTROLLER_0_AVL_CSR_IRQ 2
#define EPCQ_CONTROLLER_0_AVL_CSR_IRQ_INTERRUPT_CONTROLLER_ID 0
#define EPCQ_CONTROLLER_0_AVL_CSR_IS_EPCS 1
#define EPCQ_CONTROLLER_0_AVL_CSR_NAME "/dev/epcq_controller_0_avl_csr"
#define EPCQ_CONTROLLER_0_AVL_CSR_NUMBER_OF_SECTORS 32
#define EPCQ_CONTROLLER_0_AVL_CSR_PAGE_SIZE 256
#define EPCQ_CONTROLLER_0_AVL_CSR_SECTOR_SIZE 65536
#define EPCQ_CONTROLLER_0_AVL_CSR_SPAN 32
#define EPCQ_CONTROLLER_0_AVL_CSR_SUBSECTOR_SIZE 4096
#define EPCQ_CONTROLLER_0_AVL_CSR_TYPE "altera_epcq_controller_mod"
#define ALT_MODULE_CLASS_epcq_controller2_0_avl_csr altera_epcq_controller2
#define EPCQ_CONTROLLER2_0_AVL_CSR_BASE 0x20100
#define EPCQ_CONTROLLER2_0_AVL_CSR_FLASH_TYPE "EPCQ16"
#define EPCQ_CONTROLLER2_0_AVL_CSR_IRQ 2
#define EPCQ_CONTROLLER2_0_AVL_CSR_IRQ_INTERRUPT_CONTROLLER_ID 0
#define EPCQ_CONTROLLER2_0_AVL_CSR_IS_EPCS 0
#define EPCQ_CONTROLLER2_0_AVL_CSR_NAME "/dev/epcq_controller2_0_avl_csr"
#define EPCQ_CONTROLLER2_0_AVL_CSR_NUMBER_OF_SECTORS 32
#define EPCQ_CONTROLLER2_0_AVL_CSR_PAGE_SIZE 256
#define EPCQ_CONTROLLER2_0_AVL_CSR_SECTOR_SIZE 65536
#define EPCQ_CONTROLLER2_0_AVL_CSR_SPAN 64
#define EPCQ_CONTROLLER2_0_AVL_CSR_SUBSECTOR_SIZE 4096
#define EPCQ_CONTROLLER2_0_AVL_CSR_TYPE "altera_epcq_controller2"
/*
* epcq_controller_0_avl_mem configuration
* epcq_controller2_0_avl_mem configuration
*
*/
#define ALT_MODULE_CLASS_epcq_controller_0_avl_mem altera_epcq_controller_mod
#define EPCQ_CONTROLLER_0_AVL_MEM_BASE 0x800000
#define EPCQ_CONTROLLER_0_AVL_MEM_FLASH_TYPE "EPCS16"
#define EPCQ_CONTROLLER_0_AVL_MEM_IRQ -1
#define EPCQ_CONTROLLER_0_AVL_MEM_IRQ_INTERRUPT_CONTROLLER_ID -1
#define EPCQ_CONTROLLER_0_AVL_MEM_IS_EPCS 1
#define EPCQ_CONTROLLER_0_AVL_MEM_NAME "/dev/epcq_controller_0_avl_mem"
#define EPCQ_CONTROLLER_0_AVL_MEM_NUMBER_OF_SECTORS 32
#define EPCQ_CONTROLLER_0_AVL_MEM_PAGE_SIZE 256
#define EPCQ_CONTROLLER_0_AVL_MEM_SECTOR_SIZE 65536
#define EPCQ_CONTROLLER_0_AVL_MEM_SPAN 2097152
#define EPCQ_CONTROLLER_0_AVL_MEM_SUBSECTOR_SIZE 4096
#define EPCQ_CONTROLLER_0_AVL_MEM_TYPE "altera_epcq_controller_mod"
#define ALT_MODULE_CLASS_epcq_controller2_0_avl_mem altera_epcq_controller2
#define EPCQ_CONTROLLER2_0_AVL_MEM_BASE 0x800000
#define EPCQ_CONTROLLER2_0_AVL_MEM_FLASH_TYPE "EPCQ16"
#define EPCQ_CONTROLLER2_0_AVL_MEM_IRQ -1
#define EPCQ_CONTROLLER2_0_AVL_MEM_IRQ_INTERRUPT_CONTROLLER_ID -1
#define EPCQ_CONTROLLER2_0_AVL_MEM_IS_EPCS 0
#define EPCQ_CONTROLLER2_0_AVL_MEM_NAME "/dev/epcq_controller2_0_avl_mem"
#define EPCQ_CONTROLLER2_0_AVL_MEM_NUMBER_OF_SECTORS 32
#define EPCQ_CONTROLLER2_0_AVL_MEM_PAGE_SIZE 256
#define EPCQ_CONTROLLER2_0_AVL_MEM_SECTOR_SIZE 65536
#define EPCQ_CONTROLLER2_0_AVL_MEM_SPAN 2097152
#define EPCQ_CONTROLLER2_0_AVL_MEM_SUBSECTOR_SIZE 4096
#define EPCQ_CONTROLLER2_0_AVL_MEM_TYPE "altera_epcq_controller_mod"
/*

42
sys.qsys
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File diff suppressed because one or more lines are too long

482
sys.sopcinfo
View File

@ -1,11 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="sys" kind="sys" version="1.0" fabric="QSYS">
<!-- Format version 19.1 670 (Future versions may contain additional information.) -->
<!-- 2020.10.03.18:14:20 -->
<!-- 2020.11.08.16:09:15 -->
<!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type>
<value>1601738060</value>
<value>1604844554</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
@ -390,12 +390,6 @@ parameters are a RESULT of the module parameters. -->
<slaveName>clock</slaveName>
<name>i2c_opencores_1.clock</name>
</clockDomainMember>
<clockDomainMember>
<isBridge>false</isBridge>
<moduleName>epcq_controller_0</moduleName>
<slaveName>clock_sink</slaveName>
<name>epcq_controller_0.clock_sink</name>
</clockDomainMember>
<clockDomainMember>
<isBridge>false</isBridge>
<moduleName>sc_config_0</moduleName>
@ -414,6 +408,12 @@ parameters are a RESULT of the module parameters. -->
<slaveName>clock_sink</slaveName>
<name>pll_reconfig_0.clock_sink</name>
</clockDomainMember>
<clockDomainMember>
<isBridge>false</isBridge>
<moduleName>epcq_controller2_0</moduleName>
<slaveName>clock_sink</slaveName>
<name>epcq_controller2_0.clock_sink</name>
</clockDomainMember>
</interface>
<interface name="clk_reset" kind="reset_source" version="19.1">
<!-- The connection points exposed by a module instance for the
@ -478,19 +478,19 @@ parameters are a RESULT of the module parameters. -->
</interface>
</module>
<module
name="epcq_controller_0"
kind="altera_epcq_controller_mod"
name="epcq_controller2_0"
kind="altera_epcq_controller2"
version="19.1"
path="epcq_controller_0">
path="epcq_controller2_0">
<!-- Describes a single module. Module parameters are
the requested settings for a module instance. -->
<assignment>
<name>embeddedsw.CMacro.FLASH_TYPE</name>
<value>EPCS16</value>
<value>EPCQ16</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.IS_EPCS</name>
<value>1</value>
<value>0</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.NUMBER_OF_SECTORS</name>
@ -630,7 +630,7 @@ the requested settings for a module instance. -->
</parameter>
<parameter name="FLASH_TYPE">
<type>java.lang.String</type>
<value>EPCS16</value>
<value>EPCQ16</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@ -652,6 +652,24 @@ the requested settings for a module instance. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="AUTO_DEVICE">
<type>java.lang.String</type>
<value>EP4CE15E22C8</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
<sysinfo_type>DEVICE</sysinfo_type>
</parameter>
<parameter name="AUTO_DEVICE_SPEEDGRADE">
<type>java.lang.String</type>
<value>8</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
<sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@ -668,112 +686,6 @@ the requested settings for a module instance. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
<interface name="clock_sink" kind="clock_sink" version="19.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="externallyDriven">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="ptfSchematicName">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="clockRateKnown">
<type>java.lang.Boolean</type>
<value>true</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="clockRate">
<type>java.lang.Long</type>
<value>27000000</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<type>clock</type>
<isStart>false</isStart>
<port>
<name>clk</name>
<direction>Input</direction>
<width>1</width>
<role>clk</role>
</port>
</interface>
<interface name="reset" kind="reset_sink" version="19.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="associatedClock">
<type>java.lang.String</type>
<value>clock_sink</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="synchronousEdges">
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
<value>DEASSERT</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>reset</type>
<isStart>false</isStart>
<port>
<name>reset_n</name>
<direction>Input</direction>
<width>1</width>
<role>reset_n</role>
</port>
</interface>
<interface name="avl_csr" kind="avalon_slave" version="19.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
@ -812,7 +724,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="addressSpan">
<type>java.math.BigInteger</type>
<value>32</value>
<value>64</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
@ -860,7 +772,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="bridgedAddressOffset">
<type>java.math.BigInteger</type>
<value></value>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
@ -1129,7 +1041,7 @@ parameters are a RESULT of the module parameters. -->
<port>
<name>avl_csr_addr</name>
<direction>Input</direction>
<width>3</width>
<width>4</width>
<role>address</role>
</port>
<port>
@ -1237,7 +1149,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="bridgedAddressOffset">
<type>java.math.BigInteger</type>
<value></value>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
@ -1546,7 +1458,7 @@ particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="associatedAddressablePoint">
<type>com.altera.entityinterfaces.IConnectionPoint</type>
<value>epcq_controller_0.avl_csr</value>
<value>epcq_controller2_0.avl_csr</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@ -1570,7 +1482,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="bridgedReceiverOffset">
<type>java.lang.Integer</type>
<value></value>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@ -1617,6 +1529,112 @@ parameters are a RESULT of the module parameters. -->
<role>irq</role>
</port>
</interface>
<interface name="clock_sink" kind="clock_sink" version="19.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="externallyDriven">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="ptfSchematicName">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="clockRateKnown">
<type>java.lang.Boolean</type>
<value>true</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="clockRate">
<type>java.lang.Long</type>
<value>27000000</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<type>clock</type>
<isStart>false</isStart>
<port>
<name>clk</name>
<direction>Input</direction>
<width>1</width>
<role>clk</role>
</port>
</interface>
<interface name="reset" kind="reset_sink" version="19.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="associatedClock">
<type>java.lang.String</type>
<value>clock_sink</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="synchronousEdges">
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
<value>DEASSERT</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>reset</type>
<isStart>false</isStart>
<port>
<name>reset_n</name>
<direction>Input</direction>
<width>1</width>
<role>reset_n</role>
</port>
</interface>
</module>
<module name="hw_crc32_0" kind="hw_crc32" version="1.0" path="hw_crc32_0">
<!-- Describes a single module. Module parameters are
@ -8933,13 +8951,6 @@ parameters are a RESULT of the module parameters. -->
<width>32</width>
<role>irq</role>
</port>
<interrupt>
<isBridge>false</isBridge>
<moduleName>epcq_controller_0</moduleName>
<slaveName>interrupt_sender</slaveName>
<name>epcq_controller_0.interrupt_sender</name>
<interruptNumber>2</interruptNumber>
</interrupt>
<interrupt>
<isBridge>false</isBridge>
<moduleName>i2c_opencores_0</moduleName>
@ -8954,6 +8965,13 @@ parameters are a RESULT of the module parameters. -->
<name>i2c_opencores_1.interrupt_sender</name>
<interruptNumber>4</interruptNumber>
</interrupt>
<interrupt>
<isBridge>false</isBridge>
<moduleName>epcq_controller2_0</moduleName>
<slaveName>interrupt_sender</slaveName>
<name>epcq_controller2_0.interrupt_sender</name>
<interruptNumber>2</interruptNumber>
</interrupt>
<interrupt>
<isBridge>false</isBridge>
<moduleName>timer_0</moduleName>
@ -9650,17 +9668,17 @@ parameters are a RESULT of the module parameters. -->
</memoryBlock>
<memoryBlock>
<isBridge>false</isBridge>
<moduleName>epcq_controller_0</moduleName>
<moduleName>epcq_controller2_0</moduleName>
<slaveName>avl_csr</slaveName>
<name>epcq_controller_0.avl_csr</name>
<name>epcq_controller2_0.avl_csr</name>
<baseAddress>131328</baseAddress>
<span>32</span>
<span>64</span>
</memoryBlock>
<memoryBlock>
<isBridge>false</isBridge>
<moduleName>epcq_controller_0</moduleName>
<moduleName>epcq_controller2_0</moduleName>
<slaveName>avl_mem</slaveName>
<name>epcq_controller_0.avl_mem</name>
<name>epcq_controller2_0.avl_mem</name>
<baseAddress>8388608</baseAddress>
<span>2097152</span>
</memoryBlock>
@ -11852,11 +11870,11 @@ parameters are a RESULT of the module parameters. -->
<endConnectionPoint>avalon_slave_0</endConnectionPoint>
</connection>
<connection
name="pulpino_0.avalon_master_lsu/epcq_controller_0.avl_csr"
name="pulpino_0.avalon_master_lsu/epcq_controller2_0.avl_csr"
kind="avalon"
version="19.1"
start="pulpino_0.avalon_master_lsu"
end="epcq_controller_0.avl_csr">
end="epcq_controller2_0.avl_csr">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@ -11899,15 +11917,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>pulpino_0</startModule>
<startConnectionPoint>avalon_master_lsu</startConnectionPoint>
<endModule>epcq_controller_0</endModule>
<endModule>epcq_controller2_0</endModule>
<endConnectionPoint>avl_csr</endConnectionPoint>
</connection>
<connection
name="pulpino_0.avalon_master_lsu/epcq_controller_0.avl_mem"
name="pulpino_0.avalon_master_lsu/epcq_controller2_0.avl_mem"
kind="avalon"
version="19.1"
start="pulpino_0.avalon_master_lsu"
end="epcq_controller_0.avl_mem">
end="epcq_controller2_0.avl_mem">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@ -11950,7 +11968,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>pulpino_0</startModule>
<startConnectionPoint>avalon_master_lsu</startConnectionPoint>
<endModule>epcq_controller_0</endModule>
<endModule>epcq_controller2_0</endModule>
<endConnectionPoint>avl_mem</endConnectionPoint>
</connection>
<connection
@ -12529,33 +12547,6 @@ parameters are a RESULT of the module parameters. -->
<endModule>i2c_opencores_1</endModule>
<endConnectionPoint>clock</endConnectionPoint>
</connection>
<connection
name="clk_27.clk/epcq_controller_0.clock_sink"
kind="clock"
version="19.1"
start="clk_27.clk"
end="epcq_controller_0.clock_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>clk_27</startModule>
<startConnectionPoint>clk</startConnectionPoint>
<endModule>epcq_controller_0</endModule>
<endConnectionPoint>clock_sink</endConnectionPoint>
</connection>
<connection
name="clk_27.clk/sc_config_0.clock_sink"
kind="clock"
@ -12638,19 +12629,11 @@ parameters are a RESULT of the module parameters. -->
<endConnectionPoint>clock_sink</endConnectionPoint>
</connection>
<connection
name="pulpino_0.interrupt_receiver/epcq_controller_0.interrupt_sender"
kind="interrupt"
name="clk_27.clk/epcq_controller2_0.clock_sink"
kind="clock"
version="19.1"
start="pulpino_0.interrupt_receiver"
end="epcq_controller_0.interrupt_sender">
<parameter name="irqNumber">
<type>int</type>
<value>2</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
start="clk_27.clk"
end="epcq_controller2_0.clock_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@ -12667,10 +12650,10 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>pulpino_0</startModule>
<startConnectionPoint>interrupt_receiver</startConnectionPoint>
<endModule>epcq_controller_0</endModule>
<endConnectionPoint>interrupt_sender</endConnectionPoint>
<startModule>clk_27</startModule>
<startConnectionPoint>clk</startConnectionPoint>
<endModule>epcq_controller2_0</endModule>
<endConnectionPoint>clock_sink</endConnectionPoint>
</connection>
<connection
name="pulpino_0.interrupt_receiver/i2c_opencores_0.interrupt_sender"
@ -12742,6 +12725,41 @@ parameters are a RESULT of the module parameters. -->
<endModule>i2c_opencores_1</endModule>
<endConnectionPoint>interrupt_sender</endConnectionPoint>
</connection>
<connection
name="pulpino_0.interrupt_receiver/epcq_controller2_0.interrupt_sender"
kind="interrupt"
version="19.1"
start="pulpino_0.interrupt_receiver"
end="epcq_controller2_0.interrupt_sender">
<parameter name="irqNumber">
<type>int</type>
<value>2</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>pulpino_0</startModule>
<startConnectionPoint>interrupt_receiver</startConnectionPoint>
<endModule>epcq_controller2_0</endModule>
<endConnectionPoint>interrupt_sender</endConnectionPoint>
</connection>
<connection
name="pulpino_0.interrupt_receiver/timer_0.irq"
kind="interrupt"
@ -12974,33 +12992,6 @@ parameters are a RESULT of the module parameters. -->
<endModule>pio_1</endModule>
<endConnectionPoint>reset</endConnectionPoint>
</connection>
<connection
name="clk_27.clk_reset/epcq_controller_0.reset"
kind="reset"
version="19.1"
start="clk_27.clk_reset"
end="epcq_controller_0.reset">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>clk_27</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
<endModule>epcq_controller_0</endModule>
<endConnectionPoint>reset</endConnectionPoint>
</connection>
<connection
name="clk_27.clk_reset/timer_0.reset"
kind="reset"
@ -13028,6 +13019,33 @@ parameters are a RESULT of the module parameters. -->
<endModule>timer_0</endModule>
<endConnectionPoint>reset</endConnectionPoint>
</connection>
<connection
name="clk_27.clk_reset/epcq_controller2_0.reset"
kind="reset"
version="19.1"
start="clk_27.clk_reset"
end="epcq_controller2_0.reset">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>clk_27</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
<endModule>epcq_controller2_0</endModule>
<endConnectionPoint>reset</endConnectionPoint>
</connection>
<connection
name="clk_27.clk_reset/onchip_memory2_0.reset1"
kind="reset"
@ -13232,26 +13250,10 @@ parameters are a RESULT of the module parameters. -->
</plugin>
<plugin>
<instanceCount>1</instanceCount>
<name>altera_epcq_controller_mod</name>
<name>altera_epcq_controller2</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IModule</subtype>
<displayName>Altera Serial Flash Controller</displayName>
<version>19.1</version>
</plugin>
<plugin>
<instanceCount>14</instanceCount>
<name>clock_sink</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Clock Input</displayName>
<version>19.1</version>
</plugin>
<plugin>
<instanceCount>14</instanceCount>
<name>reset_sink</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Reset Input</displayName>
<displayName>Serial Flash Controller II Intel FPGA IP</displayName>
<version>19.1</version>
</plugin>
<plugin>
@ -13270,6 +13272,22 @@ parameters are a RESULT of the module parameters. -->
<displayName>Interrupt Sender</displayName>
<version>19.1</version>
</plugin>
<plugin>
<instanceCount>14</instanceCount>
<name>clock_sink</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Clock Input</displayName>
<version>19.1</version>
</plugin>
<plugin>
<instanceCount>14</instanceCount>
<name>reset_sink</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Reset Input</displayName>
<version>19.1</version>
</plugin>
<plugin>
<instanceCount>1</instanceCount>
<name>hw_crc32</name>