6502
/
ossc
mirror of https://github.com/marqs85/ossc.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fix HDTV mode parameters

This commit is contained in:
marqs 2017-05-30 21:16:03 +03:00
parent 2577470abe
commit 2aee3294e3
7 changed files with 1050 additions and 1045 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
ossc.sdc
View File

@ -29,10 +29,10 @@ set_input_delay -clock pclk_hdtv -max $TVP_dmax $critinputs
set_input_delay -clock pclk_sdtv -min $TVP_dmin $critinputs -add_delay
set_input_delay -clock pclk_sdtv -max $TVP_dmax $critinputs -add_delay
# output delay constraints (TODO: investigate why adding vsync upsets timing analyzer)
# output delay constraints
set IT_Tsu 1.0
set IT_Th -0.5
set critoutputs_hdmi [get_ports {HDMI_TX_RD* HDMI_TX_GD* HDMI_TX_BD* HDMI_TX_DE HDMI_TX_HS}]
set critoutputs_hdmi [get_ports {HDMI_TX_RD* HDMI_TX_GD* HDMI_TX_BD* HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_hdtv -min $IT_Th $critoutputs_hdmi
set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_hdtv -max $IT_Tsu $critoutputs_hdmi
set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_2x -min $IT_Th $critoutputs_hdmi -add_delay

101
rtl/scanconverter.v
View File

@ -134,9 +134,9 @@ reg [2:0] pclk_5x_cnt;
//configuration registers
reg [10:0] H_ACTIVE; //max. 2047
reg [8:0] H_BACKPORCH; //max. 511
reg [9:0] H_AVIDSTART; //max. 1023
reg [10:0] V_ACTIVE; //max. 2047
reg [5:0] V_BACKPORCH; //max. 63
reg [6:0] V_AVIDSTART; //max. 127
reg [7:0] H_SYNCLEN;
reg [2:0] V_SYNCLEN;
reg [1:0] V_SCANLINEMODE;
@ -343,14 +343,17 @@ pll_3x pll_linetriple (
.locked ( pclk_3x_lock )
);
wire [11:0] linebuf_rdaddr = linebuf_hoffset-H_AVIDSTART;
wire [11:0] linebuf_wraddr = hcnt_1x-H_AVIDSTART;
//TODO: add secondary buffers for interlaced signals with alternative field order
linebuf linebuf_rgb (
.data({R_in_L, G_in_L, B_in_L}),
.rdaddress ( linebuf_hoffset + (~line_idx << 11) ),
.rdaddress ( {~line_idx, linebuf_rdaddr[10:0]} ),
.rdclock ( linebuf_rdclock ),
.wraddress(hcnt_1x + (line_idx << 11)),
.wraddress( {line_idx, linebuf_wraddr[10:0]} ),
.wrclock ( pclk_1x ),
.wren ( 1'b1 ),
.wren ( !linebuf_wraddr[11] ),
.q ( {R_lbuf, G_lbuf, B_lbuf} )
);
@ -362,7 +365,7 @@ always @(posedge pclk_act)
begin
line_id_pp1 <= line_id_act;
col_id_pp1 <= col_id_act;
mask_enable_pp1 <= ((hcnt_act < H_SYNCLEN+H_BACKPORCH+H_MASK) | (hcnt_act >= H_SYNCLEN+H_BACKPORCH+H_ACTIVE-H_MASK) | (vcnt_act < V_SYNCLEN+V_BACKPORCH+V_MASK) | (vcnt_act >= V_SYNCLEN+V_BACKPORCH+V_ACTIVE-V_MASK));
mask_enable_pp1 <= ((hcnt_act < H_AVIDSTART+H_MASK) | (hcnt_act >= H_AVIDSTART+H_ACTIVE-H_MASK) | (vcnt_act < V_AVIDSTART+V_MASK) | (vcnt_act >= V_AVIDSTART+V_ACTIVE-V_MASK));
HSYNC_pp2 <= HSYNC_act;
VSYNC_pp2 <= VSYNC_act;
@ -528,13 +531,13 @@ begin
H_MULTMODE <= h_info[31:30]; // Horizontal scaling mode
V_MULTMODE <= v_info[31:29]; // Line multiply mode
H_SYNCLEN <= h_info[27:20];
H_BACKPORCH <= h_info[19:11]; // Horizontal backporch length from by the CPU - 9bits (0...511)
H_ACTIVE <= h_info[10:0]; // Horizontal active length from by the CPU - 11bits (0...2047)
H_SYNCLEN <= h_info[27:20]; // Horizontal sync length (0...255)
H_AVIDSTART <= h_info[19:11] + h_info[27:20]; // Horizontal sync+backporch length (0...1023)
H_ACTIVE <= h_info[10:0]; // Horizontal active length (0...2047)
V_SYNCLEN <= v_info[19:17];
V_BACKPORCH <= v_info[16:11]; // Vertical backporch length from by the CPU, 6bits (0...64)
V_ACTIVE <= v_info[10:0]; // Vertical active length from by the CPU, 11bits (0...2047)
V_SYNCLEN <= v_info[19:17]; // Vertical sync length (0...7)
V_AVIDSTART <= v_info[16:11] + v_info[19:17]; // Vertical sync+backporch length (0...127)
V_ACTIVE <= v_info[10:0]; // Vertical active length (0...2047)
H_MASK <= h_info2[28:19];
V_MASK <= v_info[25:20];
@ -577,7 +580,7 @@ begin
VSYNC_1x <= (vcnt_1x < V_SYNCLEN) ? `VSYNC_POL : ~`VSYNC_POL;
else
VSYNC_1x <= (((vcnt_1x+1'b1) < V_SYNCLEN) | ((vcnt_1x+1'b1 == V_SYNCLEN) & (hcnt_1x <= (hmax[~line_idx]>>1)))) ? `VSYNC_POL : ~`VSYNC_POL;
DE_1x <= ((hcnt_1x >= H_SYNCLEN+H_BACKPORCH) & (hcnt_1x < H_SYNCLEN+H_BACKPORCH+H_ACTIVE)) & ((vcnt_1x >= V_SYNCLEN+V_BACKPORCH) & (vcnt_1x < V_SYNCLEN+V_BACKPORCH+V_ACTIVE));
DE_1x <= ((hcnt_1x >= H_AVIDSTART) & (hcnt_1x < H_AVIDSTART+H_ACTIVE)) & ((vcnt_1x >= V_AVIDSTART) & (vcnt_1x < V_AVIDSTART+V_ACTIVE));
FID_1x <= FID_cur;
end
end
@ -619,7 +622,7 @@ begin
HSYNC_2x <= (hcnt_2x < H_SYNCLEN) ? `HSYNC_POL : ~`HSYNC_POL;
VSYNC_2x <= (vcnt_2x < V_SYNCLEN) ? `VSYNC_POL : ~`VSYNC_POL;
DE_2x <= ((hcnt_2x >= H_SYNCLEN+H_BACKPORCH) & (hcnt_2x < H_SYNCLEN+H_BACKPORCH+H_ACTIVE)) & ((vcnt_2x >= V_SYNCLEN+V_BACKPORCH) & (vcnt_2x < V_SYNCLEN+V_BACKPORCH+V_ACTIVE));
DE_2x <= ((hcnt_2x >= H_AVIDSTART) & (hcnt_2x < H_AVIDSTART+H_ACTIVE)) & ((vcnt_2x >= V_AVIDSTART) & (vcnt_2x < V_AVIDSTART+V_ACTIVE));
end
end
@ -657,13 +660,13 @@ begin
end
end
//track pclk_3x alignment to pclk_1x rising edge (pclk_1x=1 @ 120deg & pclk_1x=0 @ 240deg)
if (((pclk_1x_prev3x == 1'b1) & (pclk_1x == 1'b0)) | (pclk_3x_cnt == 2'h2))
pclk_3x_cnt <= 0;
else
pclk_3x_cnt <= pclk_3x_cnt + 1'b1;
//track pclk_3x alignment to pclk_1x rising edge (pclk_1x=1 @ 120deg & pclk_1x=0 @ 240deg)
if (((pclk_1x_prev3x == 1'b1) & (pclk_1x == 1'b0)) | (pclk_3x_cnt == 2'h2))
pclk_3x_cnt <= 0;
else
pclk_3x_cnt <= pclk_3x_cnt + 1'b1;
pclk_1x_prev3x <= pclk_1x;
pclk_1x_prev3x <= pclk_1x;
HSYNC_3x <= (hcnt_3x < H_SYNCLEN) ? `HSYNC_POL : ~`HSYNC_POL;
if (FID_cur == `FID_EVEN)
@ -675,7 +678,7 @@ begin
VSYNC_3x <= ~`VSYNC_POL;
end
DE_3x <= ((hcnt_3x >= H_SYNCLEN+H_BACKPORCH) & (hcnt_3x < H_SYNCLEN+H_BACKPORCH+H_ACTIVE)) & ((vcnt_3x >= V_SYNCLEN+V_BACKPORCH) & (vcnt_3x < V_SYNCLEN+V_BACKPORCH+V_ACTIVE));
DE_3x <= ((hcnt_3x >= H_AVIDSTART) & (hcnt_3x < H_AVIDSTART+H_ACTIVE)) & ((vcnt_3x >= V_AVIDSTART) & (vcnt_3x < V_AVIDSTART+V_ACTIVE));
end
end
@ -686,15 +689,15 @@ begin
vcnt_4x <= 0;
line_out_idx_4x <= 0;
end else begin
// TODO: better implementation
if ((DE_3x == 1) & (DE_3x_prev4x == 0))
hcnt_4x_aspfix <= hcnt_3x - 160;
else
hcnt_4x_aspfix <= hcnt_4x_aspfix + 1'b1;
DE_3x_prev4x <= DE_3x;
// TODO: better implementation
if ((DE_3x == 1) & (DE_3x_prev4x == 0))
hcnt_4x_aspfix <= hcnt_3x - 160;
else
hcnt_4x_aspfix <= hcnt_4x_aspfix + 1'b1;
DE_3x_prev4x <= DE_3x;
if ((pclk_4x_cnt == 0) & (line_change | frame_change)) begin //aligned with posedge of pclk_1x
hcnt_4x <= 0;
hcnt_4x_opt <= H_OPT_SAMPLE_SEL;
@ -721,18 +724,18 @@ begin
hcnt_4x_opt_ctr <= hcnt_4x_opt_ctr + 1'b1;
end
end
//track pclk_4x alignment to pclk_1x rising edge (pclk_1x=1 @ 180deg & pclk_1x=0 @ 270deg)
if (((pclk_1x_prev4x == 1'b1) & (pclk_1x == 1'b0)) | (pclk_4x_cnt == 2'h3))
pclk_4x_cnt <= 0;
else
pclk_4x_cnt <= pclk_4x_cnt + 1'b1;
pclk_1x_prev4x <= pclk_1x;
//track pclk_4x alignment to pclk_1x rising edge (pclk_1x=1 @ 180deg & pclk_1x=0 @ 270deg)
if (((pclk_1x_prev4x == 1'b1) & (pclk_1x == 1'b0)) | (pclk_4x_cnt == 2'h3))
pclk_4x_cnt <= 0;
else
pclk_4x_cnt <= pclk_4x_cnt + 1'b1;
pclk_1x_prev4x <= pclk_1x;
HSYNC_4x <= (hcnt_4x < H_SYNCLEN) ? `HSYNC_POL : ~`HSYNC_POL;
VSYNC_4x <= (vcnt_4x < V_SYNCLEN) ? `VSYNC_POL : ~`VSYNC_POL;
DE_4x <= ((hcnt_4x >= H_SYNCLEN+H_BACKPORCH) & (hcnt_4x < H_SYNCLEN+H_BACKPORCH+H_ACTIVE)) & ((vcnt_4x >= V_SYNCLEN+V_BACKPORCH) & (vcnt_4x < V_SYNCLEN+V_BACKPORCH+V_ACTIVE));
DE_4x <= ((hcnt_4x >= H_AVIDSTART) & (hcnt_4x < H_AVIDSTART+H_ACTIVE)) & ((vcnt_4x >= V_AVIDSTART) & (vcnt_4x < V_AVIDSTART+V_ACTIVE));
end
end
@ -768,20 +771,20 @@ begin
end
end
//track pclk_5x alignment to pclk_1x rising edge (pclk_1x=1 @ 144deg & pclk_1x=0 @ 216deg & pclk_1x=0 @ 288deg)
if (((pclk_1x_prevprev5x == 1'b1) & (pclk_1x_prev5x == 1'b0)) | (pclk_5x_cnt == 3'h4))
pclk_5x_cnt <= 0;
else
pclk_5x_cnt <= pclk_5x_cnt + 1'b1;
pclk_1x_prev5x <= pclk_1x;
pclk_1x_prevprev5x <= pclk_1x_prev5x;
hcnt_5x_hscomp <= hcnt_5x + 11'd121;
//track pclk_5x alignment to pclk_1x rising edge (pclk_1x=1 @ 144deg & pclk_1x=0 @ 216deg & pclk_1x=0 @ 288deg)
if (((pclk_1x_prevprev5x == 1'b1) & (pclk_1x_prev5x == 1'b0)) | (pclk_5x_cnt == 3'h4))
pclk_5x_cnt <= 0;
else
pclk_5x_cnt <= pclk_5x_cnt + 1'b1;
pclk_1x_prev5x <= pclk_1x;
pclk_1x_prevprev5x <= pclk_1x_prev5x;
hcnt_5x_hscomp <= hcnt_5x + 11'd121;
HSYNC_5x <= (hcnt_5x < H_SYNCLEN) ? `HSYNC_POL : ~`HSYNC_POL;
VSYNC_5x <= (vcnt_5x < V_SYNCLEN) ? `VSYNC_POL : ~`VSYNC_POL;
DE_5x <= ((hcnt_5x >= H_SYNCLEN+H_BACKPORCH-H_L5BORDER) & (hcnt_5x < H_SYNCLEN+H_BACKPORCH+H_ACTIVE+H_L5BORDER)) & ((vcnt_5x >= V_SYNCLEN+V_BACKPORCH) & (vcnt_5x < V_SYNCLEN+V_BACKPORCH+V_ACTIVE));
DE_5x <= ((hcnt_5x >= H_AVIDSTART-H_L5BORDER) & (hcnt_5x < H_AVIDSTART+H_ACTIVE+H_L5BORDER)) & ((vcnt_5x >= V_AVIDSTART) & (vcnt_5x < V_AVIDSTART+V_ACTIVE));
end
end

1908
software/sys_controller/mem_init/sys_onchip_memory2_0.hex
View File

File diff suppressed because it is too large Load Diff

9
software/sys_controller/ossc/av_controller.c
View File

@ -367,6 +367,7 @@ void set_videoinfo()
alt_u8 sl_mode_fpga;
alt_u8 h_opt_scale = 1;
alt_u16 h_opt_startoffs = 0;
alt_u16 h_synclen = video_modes[cm.id].h_synclen;
alt_u16 h_border, h_mask;
alt_u16 v_active = video_modes[cm.id].v_active;
alt_u16 v_backporch = video_modes[cm.id].v_backporch;
@ -430,15 +431,19 @@ void set_videoinfo()
break;
}
// CEA-770.3 HDTV modes use tri-level syncs which have twice the width of bi-level syncs of corresponding CEA-861 modes
if (target_type == VIDEO_HDTV)
h_synclen *= 2;
h_border = (((cm.sample_mult-h_opt_scale)*video_modes[cm.id].h_active)/2);
h_mask = h_border + h_opt_scale*cm.cc.h_mask;
h_opt_startoffs = h_border + (cm.sample_mult-h_opt_scale)*((alt_u16)video_modes[cm.id].h_synclen+(alt_u16)video_modes[cm.id].h_backporch);
h_opt_startoffs = h_border + (cm.sample_mult-h_opt_scale)*(h_synclen+(alt_u16)video_modes[cm.id].h_backporch);
h_opt_startoffs = (h_opt_startoffs/cm.sample_mult)*cm.sample_mult;
printf("h_border: %u, h_opt_startoffs: %u\n", h_border, h_opt_startoffs);
IOWR_ALTERA_AVALON_PIO_DATA(PIO_3_BASE, (cm.fpga_hmultmode<<30) |
((cm.cc.l5_fmt!=L5FMT_1600x1200)<<29) |
((((cm.sample_mult*video_modes[cm.id].h_synclen)-cm.hsync_cut)&0xff)<<20) |
((((cm.sample_mult*h_synclen)-cm.hsync_cut)&0xff)<<20) |
(((cm.sample_mult*(alt_u16)video_modes[cm.id].h_backporch)&0x1ff)<<11) |
((cm.sample_mult*video_modes[cm.id].h_active)&0x7ff));
IOWR_ALTERA_AVALON_PIO_DATA(PIO_4_BASE, (h_mask<<19) |

65
software/sys_controller/tvp7002/video_modes.h
View File

@ -26,7 +26,7 @@
#define H_TOTAL_MIN 300
#define H_TOTAL_MAX 2300
#define H_SYNCLEN_MIN 10
#define H_SYNCLEN_MAX 200
#define H_SYNCLEN_MAX 255
#define H_BPORCH_MIN 1
#define H_BPORCH_MAX 255
#define H_ACTIVE_MIN 200
@ -87,7 +87,6 @@ typedef struct {
char name[10];
alt_u16 h_active;
alt_u16 v_active;
alt_u16 hz_x100;
alt_u16 h_total;
alt_u16 v_total;
alt_u8 h_backporch;
@ -102,47 +101,45 @@ typedef struct {
#define VIDEO_MODES_DEF { \
/* 240p modes */ \
{ "1536x240", 1536, 240, 6000, 2046, 262, 234, 15, 150, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L5_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "1280x240", 1280, 240, 6000, 1560, 262, 170, 15, 72, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "960x240", 960, 240, 6000, 1170, 262, 128, 15, 54, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "320x240", 320, 240, 6000, 426, 262, 49, 14, 31, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_320_COL | MODE_L3_320_COL | MODE_L4_320_COL | MODE_L5_320_COL) }, \
{ "256x240", 256, 240, 6000, 341, 262, 39, 14, 25, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_256_COL | MODE_L3_256_COL | MODE_L4_256_COL | MODE_L5_256_COL) }, \
{ "240p", 720, 240, 6000, 858, 262, 57, 15, 62, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
{ "1536x240", 1536, 240, 2046, 262, 234, 15, 150, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L5_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "1280x240", 1280, 240, 1560, 262, 170, 15, 72, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "960x240", 960, 240, 1170, 262, 128, 15, 54, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "320x240", 320, 240, 426, 262, 49, 14, 31, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_320_COL | MODE_L3_320_COL | MODE_L4_320_COL | MODE_L5_320_COL) }, \
{ "256x240", 256, 240, 341, 262, 39, 14, 25, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_256_COL | MODE_L3_256_COL | MODE_L4_256_COL | MODE_L5_256_COL) }, \
{ "240p", 720, 240, 858, 262, 57, 15, 62, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
/* 288p modes */ \
{ "1536x240L", 1536, 240, 5000, 2046, 312, 234, 41, 150, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L5_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "1280x288", 1280, 288, 5000, 1560, 312, 170, 15, 72, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "960x288", 960, 288, 5000, 1170, 312, 128, 15, 54, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "320x240LB", 320, 240, 5000, 426, 312, 49, 41, 31, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_320_COL | MODE_L3_320_COL | MODE_L4_320_COL | MODE_L5_320_COL) }, \
{ "256x240LB", 256, 240, 5000, 341, 312, 39, 41, 25, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_256_COL | MODE_L3_256_COL | MODE_L4_256_COL | MODE_L5_256_COL) }, \
{ "288p", 720, 288, 5000, 864, 312, 69, 19, 63, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
{ "1536x240L", 1536, 240, 2046, 312, 234, 41, 150, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L5_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "1280x288", 1280, 288, 1560, 312, 170, 15, 72, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "960x288", 960, 288, 1170, 312, 128, 15, 54, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "320x240LB", 320, 240, 426, 312, 49, 41, 31, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_320_COL | MODE_L3_320_COL | MODE_L4_320_COL | MODE_L5_320_COL) }, \
{ "256x240LB", 256, 240, 341, 312, 39, 41, 25, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_256_COL | MODE_L3_256_COL | MODE_L4_256_COL | MODE_L5_256_COL) }, \
{ "288p", 720, 288, 864, 312, 69, 19, 63, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
/* 384p: Sega Model 2 */ \
{ "384p", 496, 384, 5766, 640, 423, 50, 29, 62, 3, (VIDEO_EDTV), GROUP_384P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
{ "384p", 496, 384, 640, 423, 50, 29, 62, 3, (VIDEO_EDTV), GROUP_384P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
/* 384p: X68k @ 24kHz */ \
{ "640x384", 640, 384, 5500, 800, 492, 48, 63, 96, 2, VIDEO_PC, GROUP_384P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
{ "640x384", 640, 384, 800, 492, 48, 63, 96, 2, VIDEO_PC, GROUP_384P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
/* ~525-line modes */ \
{ "480i", 720, 240, 5994, 858, 525, 57, 15, 62, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_480I, (MODE_PT | MODE_L2 | MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2 | MODE_INTERLACED) }, \
{ "480p", 720, 480, 5994, 858, 525, 60, 30, 62, 6, (VIDEO_EDTV | VIDEO_PC), GROUP_DTV480P, (MODE_PT | MODE_L2) }, \
{ "640x480", 640, 480, 6000, 800, 525, 48, 33, 96, 2, (VIDEO_PC | VIDEO_EDTV), GROUP_VGA480P, (MODE_PT | MODE_L2) }, \
{ "480i", 720, 240, 858, 525, 57, 15, 62, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_480I, (MODE_PT | MODE_L2 | MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2 | MODE_INTERLACED) }, \
{ "480p", 720, 480, 858, 525, 60, 30, 62, 6, (VIDEO_EDTV | VIDEO_PC), GROUP_DTV480P, (MODE_PT | MODE_L2) }, \
{ "640x480", 640, 480, 800, 525, 48, 33, 96, 2, (VIDEO_PC | VIDEO_EDTV), GROUP_VGA480P, (MODE_PT | MODE_L2) }, \
/* X68k @ 31kHz */ \
{ "640x512", 640, 512, 6000, 800, 568, 48, 28, 96, 2, VIDEO_PC, GROUP_NONE, MODE_PT }, \
{ "640x512", 640, 512, 800, 568, 48, 28, 96, 2, VIDEO_PC, GROUP_NONE, MODE_PT }, \
/* ~625-line modes */ \
{ "576i", 720, 288, 5000, 864, 625, 69, 19, 63, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_480I, (MODE_PT | MODE_L2 | MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2 | MODE_INTERLACED) }, \
{ "576p", 720, 576, 5000, 864, 625, 68, 39, 64, 5, VIDEO_EDTV, GROUP_DTV480P, (MODE_PT | MODE_L2) }, \
{ "800x600", 800, 600, 6000, 1056, 628, 88, 23, 128, 4, VIDEO_PC, GROUP_NONE, MODE_PT }, \
{ "576i", 720, 288, 864, 625, 69, 19, 63, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_480I, (MODE_PT | MODE_L2 | MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2 | MODE_INTERLACED) }, \
{ "576p", 720, 576, 864, 625, 68, 39, 64, 5, VIDEO_EDTV, GROUP_DTV480P, (MODE_PT | MODE_L2) }, \
{ "800x600", 800, 600, 1056, 628, 88, 23, 128, 4, VIDEO_PC, GROUP_NONE, MODE_PT }, \
/* 720p modes */ \
{ "720p", 1280, 720, 5994, 1650, 750, 255, 20, 40, 5, VIDEO_HDTV, GROUP_NONE, MODE_PT }, \
{ "1280x720", 1280, 720, 6000, 1650, 750, 220, 20, 40, 5, VIDEO_PC, GROUP_NONE, MODE_PT }, \
{ "720p", 1280, 720, 1650, 750, 220, 20, 40, 5, (VIDEO_HDTV | VIDEO_PC), GROUP_NONE, MODE_PT }, \
/* VESA XGA and SXGA modes */ \
{ "1024x768", 1024, 768, 6000, 1344, 806, 160, 29, 136, 6, VIDEO_PC, GROUP_NONE, MODE_PT }, \
{ "1280x1024", 1280, 1024, 6000, 1688, 1066, 248, 38, 112, 3, VIDEO_PC, GROUP_NONE, MODE_PT }, \
{ "1024x768", 1024, 768, 1344, 806, 160, 29, 136, 6, VIDEO_PC, GROUP_NONE, MODE_PT }, \
{ "1280x1024", 1280, 1024, 1688, 1066, 248, 38, 112, 3, VIDEO_PC, GROUP_NONE, MODE_PT }, \
/* PS2 GSM 960i mode */ \
{ "640x960i", 640, 480, 5994, 800, 1050, 48, 33, 96, 2, (VIDEO_EDTV | VIDEO_PC), GROUP_1080I, (MODE_PT | MODE_L2 | MODE_INTERLACED) }, \
/* 1080i/p HDTV modes */ \
{ "1080i", 1920, 540, 5994, 2200, 1125, 188, 16, 44, 5, (VIDEO_HDTV | VIDEO_PC), GROUP_1080I, (MODE_PT | MODE_L2 | MODE_INTERLACED) }, \
{ "1080p", 1920, 1080, 5994, 2200, 1125, 188, 36, 44, 5, VIDEO_HDTV, GROUP_NONE, MODE_PT }, \
{ "1920x1080", 1920, 1080, 6000, 2200, 1125, 148, 36, 44, 5, VIDEO_PC, GROUP_NONE, MODE_PT }, \
/* VESA UXGA with reduced h.backporch */ \
{ "1600x1200", 1600, 1200, 6000, 2160, 1250, 255, 46, 192, 3, VIDEO_PC, GROUP_NONE, MODE_PT }, \
{ "640x960i", 640, 480, 800, 1050, 48, 33, 96, 2, (VIDEO_EDTV | VIDEO_PC), GROUP_1080I, (MODE_PT | MODE_L2 | MODE_INTERLACED) }, \
/* 1080i/p modes */ \
{ "1080i", 1920, 540, 2200, 1125, 148, 16, 44, 5, (VIDEO_HDTV | VIDEO_PC), GROUP_1080I, (MODE_PT | MODE_L2 | MODE_INTERLACED) }, \
{ "1080p", 1920, 1080, 2200, 1125, 148, 36, 44, 5, (VIDEO_HDTV | VIDEO_PC), GROUP_NONE, MODE_PT }, \
/* VESA UXGA with 49 H.backporch cycles exchanged for H.synclen */ \
{ "1600x1200", 1600, 1200, 2160, 1250, 255, 46, 241, 3, VIDEO_PC, GROUP_NONE, MODE_PT }, \
}
#define VIDEO_MODES_SIZE (sizeof((mode_data_t[])VIDEO_MODES_DEF))

4
software/sys_controller_bsp/settings.bsp
View File

@ -2,8 +2,8 @@
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
<BspType>hal</BspType>
<BspVersion>default</BspVersion>
<BspGeneratedTimeStamp>May 27, 2017 1:39:56 AM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1495838396594</BspGeneratedUnixTimeStamp>
<BspGeneratedTimeStamp>May 30, 2017 7:39:09 PM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1496162349817</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>./</BspGeneratedLocation>
<BspSettingsFile>settings.bsp</BspSettingsFile>
<SopcDesignFile>../../sys.sopcinfo</SopcDesignFile>

4
sys.sopcinfo
View File

@ -1,11 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="sys" kind="sys" version="1.0" fabric="QSYS">
<!-- Format version 17.0 595 (Future versions may contain additional information.) -->
<!-- 2017.05.27.01:37:13 -->
<!-- 2017.05.30.19:34:13 -->
<!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type>
<value>1495838232</value>
<value>1496162053</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>