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Fix line3x 4:3 mode and VGA interlace detection

This commit is contained in:
marqs 2017-02-09 23:14:24 +02:00
parent 6e043ef577
commit 2c934c9dd0
7 changed files with 940 additions and 927 deletions
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1
ossc.qsf
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@ -234,4 +234,5 @@ set_global_assignment -name CDF_FILE output_files/Chain1.cdf
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 8.0
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 2.0
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

7
rtl/ossc.v
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@ -58,7 +58,7 @@ wire h_unstable;
wire [1:0] pclk_lock;
wire [1:0] pll_lock_lost;
wire [31:0] h_info, h_info2, v_info;
wire [10:0] lines_out;
wire [10:0] lines_out, tvp_lines;
wire [1:0] fpga_vsyncgen;
wire [15:0] ir_code;
@ -199,7 +199,7 @@ sys sys_inst(
.pio_1_controls_in_export ({ir_code_cnt, 5'b00000, HDMI_TX_MODE_LL, btn_LL, ir_code}),
.pio_2_horizontal_info_out_export (h_info),
.pio_3_vertical_info_out_export (v_info),
.pio_4_linecount_in_export ({VSYNC_out, 13'h0000, fpga_vsyncgen, 5'h00, lines_out}),
.pio_4_linecount_in_export ({VSYNC_out, 2'b00, tvp_lines, fpga_vsyncgen, 5'h00, lines_out}),
.pio_5_horizontal_info2_out_export (h_info2),
);
@ -226,7 +226,8 @@ scanconverter scanconverter_inst (
.fpga_vsyncgen (fpga_vsyncgen),
.pclk_lock (pclk_lock),
.pll_lock_lost (pll_lock_lost),
.lines_out (lines_out)
.lines_out (lines_out),
.tvp_lines (tvp_lines)
);
ir_rcv ir0 (

21
rtl/scanconverter.v
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@ -76,7 +76,8 @@ module scanconverter (
output reg [1:0] fpga_vsyncgen,
output [1:0] pclk_lock,
output [1:0] pll_lock_lost,
output [10:0] lines_out
output [10:0] lines_out,
output reg [10:0] tvp_lines
);
wire pclk_1x, pclk_2x, pclk_3x, pclk_4x, pclk_5x;
@ -256,9 +257,6 @@ begin
vcnt_act = vcnt_2x_ref;
end
`V_MULTMODE_3X: begin
R_act = R_3x;
G_act = G_3x;
B_act = B_3x;
HSYNC_act = HSYNC_3x;
VSYNC_act = VSYNC_1x;
DE_act = DE_3x;
@ -267,6 +265,9 @@ begin
vcnt_act = vcnt_3x_ref;
case (H_MULTMODE)
`H_MULTMODE_FULLWIDTH: begin
R_act = R_3x;
G_act = G_3x;
B_act = B_3x;
linebuf_rdclock = pclk_3x;
linebuf_hoffset = hcnt_3x;
pclk_act = pclk_3x;
@ -274,6 +275,9 @@ begin
col_id_act = {2'b00, hcnt_3x[0]};
end
`H_MULTMODE_ASPECTFIX: begin
R_act = R_4x;
G_act = G_4x;
B_act = B_4x;
linebuf_rdclock = pclk_4x;
linebuf_hoffset = hcnt_4x_aspfix;
pclk_act = pclk_4x;
@ -281,6 +285,9 @@ begin
col_id_act = {2'b00, hcnt_4x[0]};
end
`H_MULTMODE_OPTIMIZED: begin
R_act = R_3x;
G_act = G_3x;
B_act = B_3x;
linebuf_rdclock = pclk_3x;
linebuf_hoffset = hcnt_3x_opt;
pclk_act = pclk_3x;
@ -288,6 +295,9 @@ begin
col_id_act = hcnt_3x_opt_ctr;
end
default: begin
R_act = R_3x;
G_act = G_3x;
B_act = B_3x;
linebuf_rdclock = pclk_3x;
linebuf_hoffset = hcnt_3x;
pclk_act = pclk_3x;
@ -527,6 +537,7 @@ begin
if (`VSYNC_TRAILING_EDGE) //should be checked at every pclk_1x?
begin
vcnt_1x_tvp <= 0;
tvp_lines <= vcnt_1x_tvp;
FID_prev <= FID_in;
// detect non-interlaced signal with odd-odd field signaling (TVP7002 detects it as interlaced with analog sync inputs).
@ -671,7 +682,7 @@ begin
begin
if (fpga_vsyncgen[`VSYNCGEN_GENMID_BIT] == 1'b1)
VSYNC_2x <= (vcnt_2x >= lines_1x - `VSYNCGEN_LEN) ? 1'b0 : 1'b1;
else if (vcnt_1x > V_ACTIVE)
else if (vcnt_2x_ref > V_ACTIVE)
VSYNC_2x <= VSYNC_in;
end

1822
software/sys_controller/mem_init/sys_onchip_memory2_0.hex
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File diff suppressed because it is too large Load Diff

8
software/sys_controller/ossc/av_controller.c
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@ -203,7 +203,7 @@ status_t get_status(tvp_input_t input, video_format format)
}
sync_active = tvp_check_sync(input, format);
vsyncmode = cm.sync_active ? (IORD_ALTERA_AVALON_PIO_DATA(PIO_4_BASE) >> 16) : 0;
vsyncmode = cm.sync_active ? ((IORD_ALTERA_AVALON_PIO_DATA(PIO_4_BASE) >> 16) & 0x3) : 0;
data1 = tvp_readreg(TVP_LINECNT1);
data2 = tvp_readreg(TVP_LINECNT2);
@ -211,14 +211,14 @@ status_t get_status(tvp_input_t input, video_format format)
progressive = !!(data2 & (1<<5));
cm.macrovis = !!(data2 & (1<<6));
fpga_totlines = IORD_ALTERA_AVALON_PIO_DATA(PIO_4_BASE) & 0xffff;
fpga_totlines = (IORD_ALTERA_AVALON_PIO_DATA(PIO_4_BASE) >> 17) & 0x7ff;
// NOTE: "progressive" may not have correct value if H-PLL is not locked (!cm.sync_active)
if ((vsyncmode == 0x2) || (!cm.sync_active && (totlines < MIN_LINES_INTERLACED))) {
progressive = 1;
} else if ((vsyncmode == 0x1) && fpga_totlines > ((totlines-1)*2)) {
} else if ((vsyncmode == 0x1) && (fpga_totlines > 2*(totlines-1))) {
progressive = 0;
totlines = fpga_totlines; //ugly hack
totlines = fpga_totlines/2; //compensate skipped vsync
}
valid_linecnt = check_linecnt(progressive, totlines);

4
software/sys_controller_bsp/settings.bsp
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@ -2,8 +2,8 @@
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
<BspType>hal</BspType>
<BspVersion>default</BspVersion>
<BspGeneratedTimeStamp>Feb 7, 2017 10:49:51 PM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1486500591240</BspGeneratedUnixTimeStamp>
<BspGeneratedTimeStamp>Feb 9, 2017 9:00:28 PM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1486666828834</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>./</BspGeneratedLocation>
<BspSettingsFile>settings.bsp</BspSettingsFile>
<SopcDesignFile>../../sys.sopcinfo</SopcDesignFile>

4
sys.sopcinfo
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@ -1,11 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="sys" kind="sys" version="1.0" fabric="QSYS">
<!-- Format version 16.1 196 (Future versions may contain additional information.) -->
<!-- 2017.02.07.22:47:41 -->
<!-- 2017.02.09.21:58:10 -->
<!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type>
<value>1486500460</value>
<value>1486670290</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>