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* R/G/B gain/offset controls added

Browse Source 
* misc optimizations
This commit is contained in:
marqs 2016-08-20 15:54:28 +03:00
parent 827df7930f
commit 2dee0a2eb5
11 changed files with 956 additions and 949 deletions
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2
ossc.qsf
View File

@ -193,7 +193,7 @@ set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
set_global_assignment -name OPTIMIZATION_MODE BALANCED
set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
set_global_assignment -name ALLOW_REGISTER_RETIMING OFF
set_global_assignment -name ENABLE_OCT_DONE OFF

5
ossc.sdc
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@ -77,7 +77,10 @@ set_false_path -from pclk_3x_M1 -through $clkmuxnodes -to pclk_4x_M1
set_false_path -from [get_cells {scanconverter_inst|H_* scanconverter_inst|V_* scanconverter:scanconverter_inst|lines_*}]
# Ignore paths from registers which are updated only at the end of hsync
set_false_path -from [get_cells {scanconverter:scanconverter_inst|vcnt_* scanconverter:scanconverter_inst|line_idx scanconverter:scanconverter_inst|line_out_idx*}]
set_false_path -from [get_cells {scanconverter:scanconverter_inst|vcnt_* scanconverter:scanconverter_inst|line_idx scanconverter:scanconverter_inst|line_out_idx* scanconverter:scanconverter_inst|HSYNC_start*}]
# Ignore paths to registers which do not drive critical logic
set_false_path -to [get_cells {scanconverter:scanconverter_inst|line_out_idx*}]
# Ignore following clock transfers
set_false_path -from [get_clocks pclk_2x] -to [get_clocks pclk_sdtv]

1718
software/sys_controller/mem_init/sys_onchip_memory2_0.hex
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File diff suppressed because it is too large Load Diff

12
software/sys_controller/ossc/av_controller.c
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@ -120,11 +120,10 @@ void set_lpf(alt_u8 lpf)
break;
case VIDEO_SDTV:
case VIDEO_LDTV:
default:
tvp_set_lpf(0);
ths_set_lpf(0);
break;
default:
break;
}
} else {
tvp_set_lpf((tc.video_lpf == 2) ? 0x0F : 0);
@ -255,9 +254,6 @@ status_t get_status(tvp_input_t input, video_format format)
if (tc.vsync_thold != cm.cc.vsync_thold)
tvp_set_ssthold(tc.vsync_thold);
if (tc.sd_sync_win != cm.cc.sd_sync_win)
tvp_setup_glitchstripper(target_type, tc.sd_sync_win);
if ((tc.pre_coast != cm.cc.pre_coast) || (tc.post_coast != cm.cc.post_coast))
tvp_set_hpllcoast(tc.pre_coast, tc.post_coast);
@ -270,8 +266,8 @@ status_t get_status(tvp_input_t input, video_format format)
if (tc.sync_lpf != cm.cc.sync_lpf)
tvp_set_sync_lpf(tc.sync_lpf);
if (tc.en_alc != cm.cc.en_alc)
tvp_set_alc(tc.en_alc, target_type);
if (!memcmp(&tc.col, &cm.cc.col, sizeof(color_setup_t)))
tvp_set_fine_gain_offset(&cm.cc.col);
cm.cc = tc;
@ -370,7 +366,7 @@ void program_mode()
printf("Mode %s selected\n", video_modes[cm.id].name);
tvp_source_setup(cm.id, target_type, cm.cc.en_alc, (cm.progressive ? cm.totlines : cm.totlines/2), v_hz_x100/100, cm.cc.pre_coast, cm.cc.post_coast, cm.cc.vsync_thold, cm.cc.sd_sync_win);
tvp_source_setup(cm.id, target_type, (cm.progressive ? cm.totlines : cm.totlines/2), v_hz_x100/100, cm.cc.pre_coast, cm.cc.post_coast, cm.cc.vsync_thold);
set_lpf(cm.cc.video_lpf);
set_videoinfo();
}

22
software/sys_controller/ossc/avconfig.c
View File

@ -28,6 +28,8 @@
#define DEFAULT_POST_COAST 0
#define DEFAULT_SAMPLER_PHASE 16
#define DEFAULT_SYNC_VTH 11
#define DEFAULT_FINE_GAIN 26
#define DEFAULT_FINE_OFFSET 0x80
extern mode_data_t video_modes[], video_modes_def[];
extern alt_u8 video_mode_cnt;
@ -37,13 +39,19 @@ avconfig_t tc;
// Default configuration
const avconfig_t tc_default = {
.sampler_phase = DEFAULT_SAMPLER_PHASE,
.sync_vth = DEFAULT_SYNC_VTH,
.vsync_thold = DEFAULT_VSYNC_THOLD,
.sd_sync_win = DEFAULT_SD_SYNC_WIN,
.en_alc = 1,
.pre_coast = DEFAULT_PRE_COAST,
.post_coast = DEFAULT_POST_COAST,
.sampler_phase = DEFAULT_SAMPLER_PHASE,
.sync_vth = DEFAULT_SYNC_VTH,
.vsync_thold = DEFAULT_VSYNC_THOLD,
.pre_coast = DEFAULT_PRE_COAST,
.post_coast = DEFAULT_POST_COAST,
.col = {
.r_f_gain = DEFAULT_FINE_GAIN,
.g_f_gain = DEFAULT_FINE_GAIN,
.b_f_gain = DEFAULT_FINE_GAIN,
.r_f_off = DEFAULT_FINE_OFFSET,
.g_f_off = DEFAULT_FINE_OFFSET,
.b_f_off = DEFAULT_FINE_OFFSET,
},
};
int set_default_avconfig()

4
software/sys_controller/ossc/avconfig.h
View File

@ -21,6 +21,7 @@
#define AVCONFIG_H_
#include "alt_types.h"
#include "tvp7002.h"
#define SCANLINESTR_MAX 15
#define HV_MASK_MAX 63
@ -51,15 +52,14 @@ typedef struct {
alt_u8 ypbpr_cs;
alt_u8 sync_vth;
alt_u8 vsync_thold;
alt_u8 sd_sync_win;
alt_u8 sync_lpf;
alt_u8 video_lpf;
alt_u8 en_alc;
alt_u8 pre_coast;
alt_u8 post_coast;
alt_u8 edtv_l2x;
alt_u8 interlace_pt;
alt_u8 def_input;
color_setup_t col;
} __attribute__((packed)) avconfig_t;
int set_default_avconfig();

31
software/sys_controller/ossc/menu.c
View File

@ -55,6 +55,7 @@ static void extclks_to_time_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1,
static void sl_str_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%u%%", ((v+1)*625)/100); }
static void lines_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%u lines", v); }
static void pixels_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%u pixels", v); }
static void value_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, " %u", v); }
MENU(menu_advtiming, P99_PROTECT({ \
{ "H. samplerate", OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_h_samplerate, H_TOTAL_MIN, H_TOTAL_MAX, vm_tweak } } },
@ -67,21 +68,25 @@ MENU(menu_advtiming, P99_PROTECT({ \
MENU(menu_vinputproc, P99_PROTECT({ \
{ "Video LPF", OPT_AVCONFIG_SELECTION, { .sel = { &tc.video_lpf, OPT_WRAP, SETTING_ITEM(video_lpf_desc) } } },
{ "YPbPr in ColSpa", OPT_AVCONFIG_SELECTION, { .sel = { &tc.ypbpr_cs, OPT_WRAP, SETTING_ITEM(ypbpr_cs_desc) } } },
{ "Auto lev. ctrl", OPT_AVCONFIG_SELECTION, { .sel = { &tc.en_alc, OPT_WRAP, SETTING_ITEM(off_on_desc) } } },
{ "Video LPF", OPT_AVCONFIG_SELECTION, { .sel = { &tc.video_lpf, OPT_WRAP, SETTING_ITEM(video_lpf_desc) } } },
{ "YPbPr in ColSpa", OPT_AVCONFIG_SELECTION, { .sel = { &tc.ypbpr_cs, OPT_WRAP, SETTING_ITEM(ypbpr_cs_desc) } } },
{ "R. offset", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.col.r_f_off, OPT_NOWRAP, 0, 0xFF, value_disp } } },
{ "G. offset", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.col.g_f_off, OPT_NOWRAP, 0, 0xFF, value_disp } } },
{ "B. offset", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.col.b_f_off, OPT_NOWRAP, 0, 0xFF, value_disp } } },
{ "R. gain", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.col.r_f_gain, OPT_NOWRAP, 0, 0xFF, value_disp } } },
{ "G. gain", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.col.g_f_gain, OPT_NOWRAP, 0, 0xFF, value_disp } } },
{ "B. gain", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.col.b_f_gain, OPT_NOWRAP, 0, 0xFF, value_disp } } },
}))
MENU(menu_sampling, P99_PROTECT({ \
{ "Sampling phase", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.sampler_phase, OPT_NOWRAP, 0, SAMPLER_PHASE_MAX, sampler_phase_disp } } },
{ "480p in sampler", OPT_AVCONFIG_SELECTION, { .sel = { &tc.s480p_mode, OPT_WRAP, SETTING_ITEM(s480p_mode_desc) } } },
{ "<Adv. timing >", OPT_SUBMENU, { .sub = { &menu_advtiming, vm_display } } }, \
{ "<Adv. timing >", OPT_SUBMENU, { .sub = { &menu_advtiming, vm_display } } },
}))
MENU(menu_sync, P99_PROTECT({ \
{ "Analog sync LPF", OPT_AVCONFIG_SELECTION, { .sel = { &tc.sync_lpf, OPT_WRAP, SETTING_ITEM(sync_lpf_desc) } } },
{ "Analog sync Vth", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.sync_vth, OPT_NOWRAP, 0, SYNC_VTH_MAX, sync_vth_disp } } },
{ "Hsync window len", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.sd_sync_win, OPT_NOWRAP, 0, SD_SYNC_WIN_MAX, extclks_to_time_disp } } },
{ "Vsync threshold", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.vsync_thold, OPT_NOWRAP, VSYNC_THOLD_MIN, VSYNC_THOLD_MAX, intclks_to_time_disp } } },
{ "H-PLL Pre-Coast", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.pre_coast, OPT_NOWRAP, 0, PLL_COAST_MAX, lines_disp } } },
{ "H-PLL Post-Coast", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.post_coast, OPT_NOWRAP, 0, PLL_COAST_MAX, lines_disp } } },
@ -107,14 +112,14 @@ MENU(menu_postproc, P99_PROTECT({ \
MENU(menu_main, P99_PROTECT({ \
{ "Video in proc >", OPT_SUBMENU, { .sub = { &menu_vinputproc, NULL } } }, \
{ "Sampling opt. >", OPT_SUBMENU, { .sub = { &menu_sampling, NULL } } }, \
{ "Sync opt. >", OPT_SUBMENU, { .sub = { &menu_sync, NULL } } }, \
{ "Output opt. >", OPT_SUBMENU, { .sub = { &menu_output, NULL } } }, \
{ "Post-proc. >", OPT_SUBMENU, { .sub = { &menu_postproc, NULL } } }, \
{ "<Fw. update >", OPT_FUNC_CALL, { .fun = { fw_update, "OK - pls restart" } } }, \
{ "<Reset settings>", OPT_FUNC_CALL, { .fun = { set_default_avconfig, "Reset done" } } }, \
{ "<Save settings >", OPT_FUNC_CALL, { .fun = { write_userdata, "Saved" } } }, \
{ "Video in proc >", OPT_SUBMENU, { .sub = { &menu_vinputproc, NULL } } },
{ "Sampling opt. >", OPT_SUBMENU, { .sub = { &menu_sampling, NULL } } },
{ "Sync opt. >", OPT_SUBMENU, { .sub = { &menu_sync, NULL } } },
{ "Output opt. >", OPT_SUBMENU, { .sub = { &menu_output, NULL } } },
{ "Post-proc. >", OPT_SUBMENU, { .sub = { &menu_postproc, NULL } } },
{ "<Fw. update >", OPT_FUNC_CALL, { .fun = { fw_update, "OK - pls restart" } } },
{ "<Reset settings>", OPT_FUNC_CALL, { .fun = { set_default_avconfig, "Reset done" } } },
{ "<Save settings >", OPT_FUNC_CALL, { .fun = { write_userdata, "Saved" } } },
}))
// Max 3 levels currently

87
software/sys_controller/tvp7002/tvp7002.c
View File

@ -43,17 +43,16 @@ extern mode_data_t video_modes[];
static void tvp_set_clamp(video_format fmt)
{
switch (fmt) {
case FORMAT_RGBS:
case FORMAT_RGBHV:
case FORMAT_RGsB:
//select bottom clamp (RGB)
tvp_writereg(TVP_SOGTHOLD, 0x58);
break;
case FORMAT_YPbPr:
//select mid clamp for Pb & Pr
tvp_writereg(TVP_SOGTHOLD, 0x5D);
break;
case FORMAT_RGBS:
case FORMAT_RGBHV:
case FORMAT_RGsB:
default:
//select bottom clamp (RGB)
tvp_writereg(TVP_SOGTHOLD, 0x58);
break;
}
}
@ -65,17 +64,16 @@ static void tvp_set_clamp_position(video_type type)
tvp_writereg(TVP_CLAMPSTART, 0x2);
tvp_writereg(TVP_CLAMPWIDTH, 0x6);
break;
case VIDEO_SDTV:
case VIDEO_EDTV:
case VIDEO_PC:
tvp_writereg(TVP_CLAMPSTART, 0x6);
tvp_writereg(TVP_CLAMPWIDTH, 0x10);
break;
case VIDEO_HDTV:
tvp_writereg(TVP_CLAMPSTART, 0x32);
tvp_writereg(TVP_CLAMPWIDTH, 0x20);
break;
case VIDEO_SDTV:
case VIDEO_EDTV:
case VIDEO_PC:
default:
tvp_writereg(TVP_CLAMPSTART, 0x6);
tvp_writereg(TVP_CLAMPWIDTH, 0x10);
break;
}
}
@ -167,6 +165,9 @@ void tvp_init()
// Increase line length tolerance
tvp_writereg(TVP_LINELENTOL, 0x06);
// Minimize HSYNC window for best sync stability
tvp_writereg(TVP_MVSWIDTH, 0x03);
// Common sync separator threshold
// Some arcade games need more that the default 0x40
tvp_set_ssthold(DEFAULT_VSYNC_THOLD);
@ -176,9 +177,15 @@ void tvp_init()
tvp_writereg(TVP_R_CGAIN, 0x08);
//set rest of the gain digitally (fine) to utilize 100% of the range at the output (0.91*(1+(26/256)) = 1)
tvp_writereg(TVP_R_FGAIN, 26);
tvp_writereg(TVP_G_FGAIN, 26);
tvp_writereg(TVP_B_FGAIN, 26);
}
void tvp_set_fine_gain_offset(color_setup_t *col) {
tvp_writereg(TVP_R_FGAIN, col->r_f_gain);
tvp_writereg(TVP_G_FGAIN, col->g_f_gain);
tvp_writereg(TVP_B_FGAIN, col->b_f_gain);
tvp_writereg(TVP_R_FOFFSET_MSB, col->r_f_off);
tvp_writereg(TVP_G_FOFFSET_MSB, col->g_f_off);
tvp_writereg(TVP_B_FOFFSET_MSB, col->b_f_off);
}
// Configure H-PLL (sampling rate, VCO gain and charge pump current)
@ -303,15 +310,14 @@ void tvp_set_alc(alt_u8 en_alc, video_type type)
case VIDEO_LDTV:
tvp_writereg(TVP_ALCPLACE, 0x9);
break;
case VIDEO_SDTV:
case VIDEO_EDTV:
case VIDEO_PC:
tvp_writereg(TVP_ALCPLACE, 0x18);
break;
case VIDEO_HDTV:
tvp_writereg(TVP_ALCPLACE, 0x5A);
break;
case VIDEO_SDTV:
case VIDEO_EDTV:
case VIDEO_PC:
default:
tvp_writereg(TVP_ALCPLACE, 0x18);
break;
}
} else {
@ -319,51 +325,33 @@ void tvp_set_alc(alt_u8 en_alc, video_type type)
}
}
void tvp_setup_glitchstripper(video_type type, alt_u8 sd_winwidth)
void tvp_source_setup(alt_8 modeid, video_type type, alt_u32 vlines, alt_u8 hz, alt_u8 pre_coast, alt_u8 post_coast, alt_u8 vsync_thold)
{
// Clamp position and ALC
tvp_set_clamp_position(type);
tvp_set_alc(1, type);
tvp_set_ssthold(vsync_thold);
// Setup Macrovision stripper and H-PLL coast.
// Coast needs to be enabled when HSYNC is missing during VSYNC. Disabled only for RGBHV.
// Macrovision stripper filters out glitches and serration pulses that may occur outside of sync window (HSYNC_lead +- TVP_MVSWIDTH*37ns). Enabled for all inputs.
switch (type) {
case VIDEO_PC:
tvp_writereg(TVP_MISCCTRL4, 0x0C);
tvp_writereg(TVP_MVSWIDTH, 0x03);
break;
case VIDEO_HDTV:
tvp_writereg(TVP_MISCCTRL4, 0x08);
tvp_writereg(TVP_MVSWIDTH, 0x0E);
break;
case VIDEO_EDTV:
tvp_writereg(TVP_MISCCTRL4, 0x08);
tvp_writereg(TVP_MVSWIDTH, 0x44);
break;
case VIDEO_LDTV:
case VIDEO_SDTV:
tvp_writereg(TVP_MISCCTRL4, 0x08);
tvp_writereg(TVP_MVSWIDTH, sd_winwidth);
break;
case VIDEO_EDTV:
case VIDEO_HDTV:
default:
tvp_writereg(TVP_MISCCTRL4, 0x08);
break;
}
}
void tvp_source_setup(alt_8 modeid, video_type type, alt_u8 en_alc, alt_u32 vlines, alt_u8 hz, alt_u8 pre_coast, alt_u8 post_coast, alt_u8 vsync_thold, alt_u8 sd_sync_win)
{
// Clamp position and ALC
tvp_set_clamp_position(type);
tvp_set_alc(en_alc, type);
tvp_set_ssthold(vsync_thold);
tvp_setup_glitchstripper(type, sd_sync_win);
tvp_setup_hpll(video_modes[modeid].h_total, vlines, hz, !!(video_modes[modeid].flags & MODE_PLLDIVBY2));
//Long coast may lead to PLL frequency drift and sync loss (e.g. SNES)
/*if (video_modes[modeid].v_active < 720)
tvp_set_hpllcoast(3, 3);
else
tvp_set_hpllcoast(1, 0);*/
// Default (3,3) coast may lead to PLL jitter and sync loss (e.g. SNES)
tvp_set_hpllcoast(pre_coast, post_coast);
// Hsync output width
@ -424,7 +412,6 @@ void tvp_source_sel(tvp_input_t input, video_format fmt)
#endif
//TODO:
//clamps
//TVP_ADCSETUP
printf("\n");

16
software/sys_controller/tvp7002/tvp7002.h
View File

@ -28,7 +28,6 @@
#define I2CA_BASE I2C_OPENCORES_0_BASE
#define DEFAULT_VSYNC_THOLD 0x44
#define DEFAULT_SD_SYNC_WIN 0x88
typedef enum {
TVP_INPUT1 = 0,
@ -57,6 +56,15 @@ typedef struct {
alt_u16 B_Pr;
} ypbpr_to_rgb_csc_t;
typedef struct {
alt_u8 r_f_off;
alt_u8 g_f_off;
alt_u8 b_f_off;
alt_u8 r_f_gain;
alt_u8 g_f_gain;
alt_u8 b_f_gain;
} __attribute__((packed)) color_setup_t;
static const alt_u32 clkrate[] = {27000000, 6500000}; //in MHz
@ -76,6 +84,8 @@ inline void tvp_set_ssthold(alt_u8 vsdetect_thold);
void tvp_init();
void tvp_set_fine_gain_offset(color_setup_t *col);
void tvp_setup_hpll(alt_u16 h_samplerate, alt_u16 v_lines, alt_u8 hz, alt_u8 plldivby2);
void tvp_sel_clk(alt_u8 refclk);
@ -92,9 +102,7 @@ void tvp_set_sog_thold(alt_u8 val);
void tvp_set_alc(alt_u8 en_alc, video_type type);
void tvp_setup_glitchstripper(video_type type, alt_u8 sd_winwidth);
void tvp_source_setup(alt_8 modeid, video_type type, alt_u8 en_alc, alt_u32 vlines, alt_u8 hz, alt_u8 pre_coast, alt_u8 post_coast, alt_u8 vsync_thold, alt_u8 sd_sync_win);
void tvp_source_setup(alt_8 modeid, video_type type, alt_u32 vlines, alt_u8 hz, alt_u8 pre_coast, alt_u8 post_coast, alt_u8 vsync_thold);
void tvp_source_sel(tvp_input_t input, video_format fmt);

4
software/sys_controller_bsp/settings.bsp
View File

@ -2,8 +2,8 @@
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
<BspType>hal</BspType>
<BspVersion>default</BspVersion>
<BspGeneratedTimeStamp>Aug 16, 2016 7:41:30 PM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1471365690097</BspGeneratedUnixTimeStamp>
<BspGeneratedTimeStamp>Aug 18, 2016 11:17:40 PM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1471551460381</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>./</BspGeneratedLocation>
<BspSettingsFile>settings.bsp</BspSettingsFile>
<SopcDesignFile>../../sys.sopcinfo</SopcDesignFile>

4
sys.sopcinfo
View File

@ -1,11 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="sys" kind="sys" version="1.0" fabric="QSYS">
<!-- Format version 15.1 185 (Future versions may contain additional information.) -->
<!-- 2016.08.16.22:35:30 -->
<!-- 2016.08.20.01:49:03 -->
<!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type>
<value>1471376130</value>
<value>1471646943</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>